H. Noda, K. Inoue, H. Mattausch, T. Koide, K. Arimoto
{"title":"A cost-efficient dynamic Ternary CAM in 130 nm CMOS technology with planar complementary capacitors and TSR architecture","authors":"H. Noda, K. Inoue, H. Mattausch, T. Koide, K. Arimoto","doi":"10.1109/VLSIC.2003.1221168","DOIUrl":null,"url":null,"abstract":"A novel dynamic Ternary-CAM (TCAM) architecture with transparently scheduled refresh, address-input-free writing and planar complementary capacitors is proposed. The planar dynamic concept allows small TCAM cell size of 4.79 /spl mu/m/sup 2/ in a 130 nm CMOS technology that is about half of the static TCAM cell size, and the complementary capacitors improve the stability of conventional-DRAM-based TCAM cells. Transparently scheduled refresh and address-input-free writing make the proposed TCAM especially attractive for classifying applications in network routers.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221168","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
A novel dynamic Ternary-CAM (TCAM) architecture with transparently scheduled refresh, address-input-free writing and planar complementary capacitors is proposed. The planar dynamic concept allows small TCAM cell size of 4.79 /spl mu/m/sup 2/ in a 130 nm CMOS technology that is about half of the static TCAM cell size, and the complementary capacitors improve the stability of conventional-DRAM-based TCAM cells. Transparently scheduled refresh and address-input-free writing make the proposed TCAM especially attractive for classifying applications in network routers.