C. K. Tien, K. Lewis, R. Philhower, H.J. Greub, J. McDonald
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引用次数: 1
Abstract
F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 /spl mu/m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. Simulations have shown 400 MHz operation. The chip contains 92,340 transistors on a 7/spl times/7 mm/sup 2/ die and dissipates 3.8 W. The F-RISC/I processor exemplifies the CPU architecture, circuit design, and testing developed to fully take advantage of GaAs technology for high speed computing.<>
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