A WiMAX turbo decoder with tailbiting BIP architecture

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI:10.1109/ASPDAC.2010.5419858

H. Arai, N. Miyamoto, K. Kotani, H. Fujisawa, Takashi Ito

引用次数: 5

Abstract

A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm2 using a 0.18 µm CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

一种具有尾部BIP结构的WiMAX涡轮解码器

提出了一种用于深度流水线turbo解码器的咬尾块交错流水线(TB-BIP)方法。当管道级数增加时，传统的滑动窗口块交错管道(SW-BIP)涡轮解码器需要进行多次预热计算。然而，通过使用TB-BIP，与SW-BIP相比，热身计算减少了50%以上。我们使用0.18µm CMOS技术实现了一个TB-BIP WiMAX涡轮解码器，该解码器具有四个3.8 mm2的管道级。该芯片在99 MHz工作时达到45 Mbps/iter和3.11 nJ/b/iter。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

自引率

0.00%

发文量

期刊最新文献

Platform modeling for exploration and synthesis Application-specific 3D Network-on-Chip design using simulated allocation Rule-based optimization of reversible circuits An extension of the generalized Hamiltonian method to S-parameter descriptor systems Adaptive power management for real-time event streams