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2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献

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Technology mapping with crosstalk noise avoidance 避免串扰噪声的技术映射
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419876
Fang-Yu Fan, Hung-Ming Chen, I-Min Liu
In today's VLSI designs, crosstalk effects causing chips to fail or suffer from low yields have become one of the very essential design issues. In this paper, we attempt to reduce crosstalk noise in logic and physical synthesis stage, which is usually done in post-layout stage. We propose a technology mapping method that can reduce the crosstalk noise while meeting delay constraints. The algorithm employing a dynamic programming framework in the matching phase determines the routing of fanin nets for all the matches to estimate the track utilization in probability. These routings are stored as virtual routing maps to compute the crosstalk noise during the covering phase, which will select the crosstalk-minimal solutions satisfying the delay constraints rather than the delay-minimal ones. This problem is different from wire congestion-driven technology mapping and our experimental results are encouraging. We experiment on the benchmark circuits in 90nm process, the results show that, with 7% of area increase, our proposed approach is effective to improve the crosstalk by 28% on average, as compared to the conventional delay- and/or congestion-driven technology mapping. The overall result is better than the efforts done in post-layout stage, and has been validated by modern commercial EDA tools. In addition, this proposed approach can be applied in local technology remapping at post-placement/post-routing and ECO stages as well.
在当今的超大规模集成电路设计中,串扰效应导致芯片失效或遭受低产量已经成为非常重要的设计问题之一。在本文中,我们尝试在逻辑和物理合成阶段降低串扰噪声,这通常是在布局后阶段完成的。提出了一种既能降低串扰噪声又能满足时延限制的技术映射方法。该算法在匹配阶段采用动态规划框架确定所有匹配的fanin网的路由,以概率估计轨迹利用率。这些路由被存储为虚拟路由映射,用于计算覆盖阶段的串扰噪声,从而选择满足延迟约束的串扰最小解,而不是延迟最小解。这个问题不同于有线拥塞驱动的技术映射,我们的实验结果令人鼓舞。我们在90nm工艺的基准电路上进行了实验,结果表明,与传统的延迟和/或拥塞驱动的技术映射相比,在面积增加7%的情况下,我们提出的方法可以有效地将串扰平均提高28%。总体效果优于后布局阶段,并已通过现代商用EDA工具验证。此外,建议的方法也可应用于安置后/布线后和ECO阶段的当地技术重新绘图。
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引用次数: 3
High level event driven thermal estimation for thermal aware task allocation and scheduling 用于热感知任务分配和调度的高级事件驱动热估计
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419781
Jin Cui, D. Maskell
Thermal aware scheduling(TAS) is an important system level optimization for CMP and MPSoC. An event driven thermal estimation method which can assist dynamic TAS is proposed in this paper. The event driven thermal estimation is based upon a thermal map which is updated only when a high level event occurs. To minimize the overhead, while maintaining the estimation accuracy, the prebuilt look-up-tables and the superposition principle are used to speed up the solution of the thermal RC network. Experimental results show our method is accurate, producing thermal estimations of similar quality to existing thermal simulators, while having a considerably reduced computational complexity. Our event driven thermal estimation technique is significantly better, in terms of accuracy, than existing TAS schedulers, making it highly suitable for integration into the OS kernel.
热感知调度(TAS)是CMP和MPSoC中重要的系统级优化。提出了一种事件驱动的热估计方法,用于辅助动态热评估。事件驱动的热估计基于仅在高层事件发生时更新的热图。在保证估计精度的前提下,利用预建的查找表和叠加原理加快了热RC网络的求解速度。实验结果表明,我们的方法是准确的,产生的热估计质量与现有的热模拟器相似,同时大大降低了计算复杂度。就准确性而言,我们的事件驱动热估计技术明显优于现有的TAS调度器,因此非常适合集成到OS内核中。
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引用次数: 11
Statistical time borrowing for pulsed-latch circuit designs 脉冲锁存电路设计的统计时间借用
Pub Date : 2010-01-18 DOI: 10.5555/1899721.1899879
Seungwhun Paik, Lee-eun Yu, Youngsoo Shin
Pulsed-latch inherits the advantage of latch in less sequencing overhead while taking the advantage of flip-flop in its convenience during timing analysis. Even though this advantage comes from the fact that pulsed-latch uses a short pulse, it is still capable of a small amount of time borrowing. A problem of allocating pulse width (out of a few predefined widths), where each width is modeled by a random variable, is formulated for minimizing the clock period of pulsed-latch circuits; this is equivalent to assigning a random variable that represents the amount of time borrowed by the combinational block between each latch pair. A statistical approach is important in this problem because assuming +3σ of all pulse widths does not represent the worst case. An allocation algorithm called SPWA as well as an algorithm to compute timing yield is proposed. In experiments with 45-nm technology, compared to the case of no time borrowing, the clock period was reduced by 12.2% and 11.7% on average when the yield constraint Yc is 0.85 and 0.95, respectively; this is compared to the deterministic counterpart called DPWA, which reduced the clock period by 7.6% and 7.3%. More importantly, DPWA failed to satisfy the yield constraints in four (out of eleven) circuits while the yield constraints were always satisfied in SPWA.
脉冲锁存器继承了锁存器较少测序开销的优点,同时又利用了触发器在时序分析时的便捷性。尽管这种优势来自于脉冲锁存器使用短脉冲,但它仍然能够借用少量的时间。分配脉冲宽度(在几个预定义宽度之外)的问题,其中每个宽度由一个随机变量建模,用于最小化脉冲锁存电路的时钟周期;这相当于分配一个随机变量,表示每个锁存对之间的组合块所借用的时间量。统计方法在这个问题中很重要,因为假设所有脉冲宽度的+3σ并不代表最坏的情况。提出了一种称为SPWA的分配算法和一种计算时序收益的算法。在45纳米技术实验中,当产率约束Yc为0.85和0.95时,时钟周期比不借用时间的情况平均缩短12.2%和11.7%;这与确定性的DPWA相比较,DPWA的时钟周期分别减少了7.6%和7.3%。更重要的是,DPWA在11个电路中有4个不满足屈服约束,而SPWA在屈服约束中总是满足。
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引用次数: 14
Fault-tolerant resynthesis with dual-output LUTs 双输出lut的容错再合成
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419873
Ju-Yueh Lee, Yu Hu, R. Majumdar, Lei He, Minming Li
We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this architectural feature can be used to build redundancy for fault masking with limited area and performance overhead. Our algorithm improves reliability of a mapping by performing two basic operations: duplication (in which free configuration bits are used to duplicate a logic function whose value is obtained at the secondary output) and encoding (in which two copies of the same logic function are ANDed or ORed together in the fanout of the duplicated logic). The problem of fault tolerant post-mapping resynthesis is then formulated as the optimal duplication and encoding scheme that ensures the minimal circuit fault rate w.r.t. a stochastic single fault model. We present an ILP formulation of this problem and an efficient algorithm based on generalized network flow. On MCNC benchmarks, experimental results show that for combinational circuits the proposed approach improves mean-time-to-failure(MTTF) by 27% with 4% area overhead, and the proposed approach with explicit area redundancy improves MTTF by 113% with 36% area overhead, compared to the baseline mapping by ABC. This provides a viable fault tolerance solution for non-mission critical applications compared to TMR (triple modular redundancy) which has a 5x–6x area overhead.
我们提出了一种基于FPGA设计的容错映射后再合成,该设计利用现代FPGA架构的双输出特性来提高映射电路对故障的可靠性。新兴的FPGA架构,如Xilinx Virtex-5中的6路LUT和Altera Stratix-III中的8路alm,都有一个辅助LUT输出,允许访问未占用的SRAM位。我们表明,该架构特征可以用于在有限的面积和性能开销下构建故障屏蔽的冗余。我们的算法通过执行两个基本操作来提高映射的可靠性:复制(其中自由配置位用于复制逻辑函数,其值在次要输出处获得)和编码(其中相同逻辑函数的两个副本在复制逻辑的扇出中被and或or在一起)。然后将容错后映射再合成问题描述为保证电路故障率在随机单故障模型下最小的最佳复制和编码方案。我们给出了该问题的一个ILP公式和一个基于广义网络流的有效算法。在MCNC基准测试中,实验结果表明,与ABC基线映射相比,对于组合电路,所提出的方法在4%的面积开销下提高了平均故障时间(MTTF) 27%,而具有显式区域冗余的方法在36%的面积开销下提高了MTTF 113%。与TMR(三模块冗余)相比,这为非关键任务应用程序提供了可行的容错解决方案,TMR具有5 - 6倍的面积开销。
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引用次数: 25
Minimizing clock latency range in robust clock tree synthesis 在鲁棒时钟树合成中最小化时钟延迟范围
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419849
Wen-Hao Liu, Yih-Lang Li, Hui Chen
Given the extensive study of clock skew minimization, in the ISPD 2009 Clock Network Synthesis (CNS) Contest, clock latency range (CLR) was initially minimized across multiple supply voltages under capacitance and slew constraints. CLR approximates the summation of the clock skew and the maximum source-to-sink delay variation for multiple supply voltages. This work develops an efficient three-stage clock tree synthesis flow for CLR minimization. Firstly, a balanced clock tree with small skew is generated. Secondly, buffer insertion and wire sizing minimizes delay variation without violating the slew constraint. Finally, skew is minimized by inserting snaking wires. Experimental results reveal that the proposed flow can complete all ISPD'09 benchmark circuits and yield less CLR than the top three winners of ISPD'09 CNS contest by 59%, 52.7% and 35.4% respectively. Besides, the proposed flow can also run 5.52, 1.86, and 7.54 times faster than the top three winners of ISPD'09 CNS contest respectively.
鉴于对时钟偏差最小化的广泛研究,在ISPD 2009时钟网络合成(CNS)竞赛中,时钟延迟范围(CLR)最初在电容和电压限制下最小化多个电源电压。CLR近似于多个电源电压下时钟偏差和最大源到汇延迟变化的总和。这项工作开发了一个有效的三阶段时钟树合成流程,用于最小化CLR。首先,生成具有小偏差的均衡时钟树;其次,缓冲器插入和导线尺寸最小化延迟变化而不违反回转约束。最后,倾斜是通过插入蛇形电线最小化。实验结果表明,该流程可以完成所有ISPD'09基准电路,其CLR比ISPD'09 CNS竞赛前三名的CLR分别低59%、52.7%和35.4%。此外,该流的运行速度也比ISPD'09 CNS大赛的前三名分别快5.52倍、1.86倍和7.54倍。
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引用次数: 27
Incremental solution of power grids using random walks 基于随机游走的电网增量解
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419787
B. Boghrati, S. Sapatnekar
It is common for a designer to consider making several small changes to a power grid, corresponding to “what if” scenarios, in an attempt to improve its performance. To evaluate the effects of each incremental change, the circuit must go through incremental analysis. This paper presents a computationally efficient and accurate method for fast and accurate incremental analysis using random walks to identify a region of influence (RoI) of a change, so that this RoI can then be analyzed by any other solver. Our experimental results demonstrate the accuracy and computational efficiency of this method.
对于设计师来说,考虑对电网做出一些小的改变是很常见的,这与“如果”的情况相对应,试图提高其性能。为了评估每个增量变化的影响,电路必须进行增量分析。本文提出了一种计算效率高且精确的方法,用于快速准确的增量分析,使用随机游走来识别变化的影响区域(RoI),以便任何其他求解器可以分析该影响区域。实验结果证明了该方法的准确性和计算效率。
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引用次数: 11
On-chip power network optimization with decoupling capacitors and controlled-ESRs 带去耦电容和可控esr的片上电网优化
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419910
Wanping Zhang, Ling Zhang, A. S. Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Engin, Chung-Kuan Cheng
In this paper, we propose an efficient approach to minimize the noise on power networks via the allocation of decoupling capacitors (decap) and controlled equivalent series resistors (ESR). The controlled-ESR is introduced to reduce the on-chip power voltage fluctuation, including both voltage drop and overshoot. We formulate an optimization problem of noise minimization with the constraint of decap budget. A revised sensitivity calculation method is derived to consider both voltage drop and overshoot. The sequential quadratic programming (SQP) algorithm is adopted to solve the optimization problem where the revised sensitivity is regarded as the gradient. Experimental results show that considering voltage drop without overshoot leads to underestimating noise by 4.8%. We also demonstrate that the controlled-ESR is able to reduce the noise by 25% with the same decap budget.
在本文中,我们提出了一种有效的方法,通过分配去耦电容器(decap)和可控等效串联电阻(ESR)来最小化电网上的噪声。引入可控esr来减小片上电源电压波动,包括压降和超调。我们提出了一个以decap预算为约束的噪声最小化优化问题。推导出一种同时考虑电压降和超调的灵敏度计算方法。以修正后的灵敏度为梯度,采用序列二次规划(SQP)算法求解优化问题。实验结果表明,考虑无超调的压降会导致噪声低估4.8%。我们还证明了控制esr能够在相同的封装预算下降低25%的噪声。
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引用次数: 6
Platform modeling for exploration and synthesis 勘探与综合平台建模
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419794
A. Gerstlauer, G. Schirner
Ever increasing complexity and heterogeneity of system platforms drive the need for a move to higher levels of abstraction accompanied by corresponding design automation tools. The basis for any automated flow are well-defined design models. In this paper, we present an overview and taxonomy of platform modeling at various levels. Experiments demonstrate the benefits of fast yet accurate intermediate models at varying levels for rapid, early design space exploration. Furthermore, paired with automatic model generation and hardware/software synthesis, an automated path from specification to implementation becomes possible.
系统平台日益增加的复杂性和异构性促使人们需要向更高层次的抽象转移,并伴随着相应的设计自动化工具。任何自动化流程的基础都是定义良好的设计模型。在本文中,我们给出了在不同层次上平台建模的概述和分类。实验证明了快速而准确的中间模型在不同层次上对快速、早期的设计空间探索的好处。此外,配合自动模型生成和硬件/软件合成,从规范到实现的自动路径成为可能。
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引用次数: 2
Optimal simultaneous pin assignment and escape routing for dense PCBs 密集pcb的最佳同时引脚分配和逃逸路由
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419881
Hui Kong, Tan Yan, Martin D. F. Wong
In PCB designs, pin positions greatly affect routability of the design. State-of-the-art pin assignment algorithms are guided by simple (heuristic) metrics to estimate routability and thus have no guarantee to obtain a routable solution. In this paper, we present a novel approach to obtain a pin assignment solution that guarantees routability. We show that the problem of simultaneous pin assignment and escape routing can be solved optimally in polynomial time. We then focus on the pin assignment and escape routing for the terminals in a bus, and present algorithmic enhancements as well as discuss the tradeoffs between single-layer and multi-layer implementations. We tested our approach on a state-of-the-art industrial board with 80 buses (over 7000 nets). The pin assignment and escape routing solutions for all the 80 buses are successfully obtainted in less than 5 minutes of CPU time.
在PCB设计中,引脚位置对设计的可达性影响很大。最先进的引脚分配算法是由简单的(启发式)指标来估计可达性,因此不能保证获得可达的解决方案。在本文中,我们提出了一种新的方法来获得保证可达性的引脚分配解。我们证明了同时分配引脚和逃逸路由的问题可以在多项式时间内得到最优解决。然后,我们将重点放在总线中终端的引脚分配和逃逸路由上,并提出算法增强以及讨论单层和多层实现之间的权衡。我们在拥有80个总线(超过7000个网络)的最先进的工业板上测试了我们的方法。在不到5分钟的CPU时间内,成功地获得了所有80总线的引脚分配和逃逸路由解决方案。
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引用次数: 19
A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography 一种新的图论、多目标双版式光刻版面分解框架
Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419807
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D. Pan
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this paper, we propose a multi-objective min-cut based decomposition framework for stitch minimization, balanced density, and overlay compensation, simultaneously. The key challenge of DPL is to accomplish high quality decomposition for large-scale layouts under reasonable runtime with the following objectives: a) the number of stitches is minimized, b) the balance between two decomposed layers is maximized for further enhanced patterning, c) the impact of overlay on coupling capacitance is reduced for less timing variation. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. An additional decomposition constraints for self-overlay compensation are obtained by integer linear programming(ILP). With the constraints, global decomposition is executed by our modified FM graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures.
随着双模光刻技术(DPL)成为亚30nm光刻工艺的主要候选,我们需要一个快速且光刻友好的分解框架。在本文中,我们提出了一种多目标最小切割分解框架,用于同时实现缝线最小化、平衡密度和覆盖补偿。DPL的关键挑战是在合理的运行时间内实现大规模布局的高质量分解,目标如下:a)最小化针数,b)最大化两个分解层之间的平衡,以进一步增强图案,c)减少覆盖对耦合电容的影响,以减少时序变化。我们使用图论算法来求最小缝线插入和平衡密度。利用整数线性规划(ILP)得到了自覆盖补偿的附加分解约束。在约束条件下,采用改进的FM图划分算法进行全局分解。实验结果表明,所提出的框架具有高度可扩展性和快速性:我们可以在5分钟内以密度平衡的方式分解所有15个基准电路,而基于ilp的方法只能完成最小的5个电路。此外,我们可以消除95%以上由加铺引起的时序变化。
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引用次数: 74
期刊
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
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