Intelligent Fill Pattern and Extraction Methodology for SoC

A. Balasinski, J. Cetin
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引用次数: 4

Abstract

Uniform pattern density of physical layers of the die, such as diffusion, poly, or metals, has significant impact on electrical parameters of the product. At active level, variations in pattern density across the die translate into wide distributions of punch-through or breakdown voltages. At poly and metal levels, a non-uniform pattern density would result in poor planarity and give rise to high via resistances and poor control of the inter-layer capacitive coupling. However, at design stage, the complex functions of SoC functional blocks do not give designers enough freedom to strictly observe a predefined set of pattern density rules. Instead, the die pattern has to be made more uniform at die integration level, by global addition of fill features (waffles). While conceptually simple, this presents significant technical challenge, as the criteria for this addition are often difficult to meet. The simple but time consuming way of making pattern density uniform is based on manual drawing of dummy features over the electrical database (intellectual property, IP) of the die. A simplistic, automated approach is to add fill pattern of fixed density until it becomes close to target pattern density of the die. However, it may not be possible to equalize out all the regions even with changes in the die architecture. In addition, this approach tends to add dummy features even if unnecessary, driving towards very high pattern density. This solution is disadvantageous for RF/analog products the performance of which can be compromised by the capacitive coupling through the waffles. The methodology proposed that the initial die pattern density is first evaluated followed by the adjustable, intelligent fill of dynamic density at the block level. This way, it is possible to keep the original pattern density and work only on the areas of small density. The authors propose that the standard cell methodology should enable pre-die level modifications of pattern density and its extraction, to ensure that all the required blocks could be placed on the product and that their parasitics are properly extracted
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SoC的智能填充模式及提取方法
模具物理层(如扩散层、聚层或金属层)的均匀图案密度对产品的电气参数有重要影响。在主动水平上,在整个模具图案密度的变化转化为广泛分布的穿孔或击穿电压。在多金属和金属水平上,不均匀的图案密度将导致较差的平面性,并导致高过通阻和层间电容耦合控制不良。然而,在设计阶段,SoC功能块的复杂功能并没有给设计师足够的自由来严格遵守预定义的模式密度规则集。相反,模具图案必须在模具集成水平上更加统一,通过全球添加填充特征(华夫饼)。虽然概念上很简单,但这提出了重大的技术挑战,因为这种添加的标准通常难以满足。使图案密度均匀的简单但耗时的方法是基于模具电气数据库(知识产权,IP)手动绘制假人特征。一种简单的自动化方法是添加固定密度的填充图案,直到它接近模具的目标图案密度。然而,它可能不可能均衡出所有的区域,即使在模具结构的变化。此外,这种方法倾向于添加虚拟特征,即使没有必要,也会导致非常高的模式密度。这种解决方案对于射频/模拟产品是不利的,这些产品的性能可能会受到通过华夫饼的电容耦合的影响。该方法提出,首先评估初始模具图案密度,然后在块水平上进行动态密度的可调智能填充。这样,就有可能保持原来的图案密度,只在密度小的区域上工作。作者建议,标准细胞方法应该能够在模前水平修改图案密度及其提取,以确保所有所需的块都可以放置在产品上,并且它们的寄生物被正确提取
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