Embedded system for area measurement using FPGA

A. F. Torres-Monsalve, J. D. Bolanos-Jojoa, Jaime Velasco-Medina
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引用次数: 1

Abstract

Area measurement is intensively used in the industry to classify objects by its size. This paper presents the hardware design of an embedded system for area measurement using image processing by considering high accuracy, high reliability and minimal time processing. In this case, the hardware implementation algorithms for image processing are described using generic structural VHDL, synthesized on the FPGA EP2C70F896C6N, and verified using an image acquisition system based on the D5M camera and the DE2-70 development kit.
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基于FPGA的嵌入式面积测量系统
面积测量在工业中被广泛用于根据物体的大小对其进行分类。从高精度、高可靠性和最短处理时间的角度出发,提出了一种基于图像处理的嵌入式面积测量系统的硬件设计。在这种情况下,使用通用结构化VHDL描述了图像处理的硬件实现算法,在FPGA EP2C70F896C6N上进行了合成,并使用基于D5M摄像机和DE2-70开发套件的图像采集系统进行了验证。
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