H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H. Cho, K. Rim, S. Kwon
{"title":"Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint","authors":"H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H. Cho, K. Rim, S. Kwon","doi":"10.1109/vlsitechnologyandcir46769.2022.9830184","DOIUrl":null,"url":null,"abstract":"We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV<sup>2</sup>) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (V<inf>min</inf>) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV<sup>2</sup>. For the first time, we have demonstrated V<inf>min</inf> of 1-fin F/F same as 2-fin one and 27% CV<sup>2</sup> reduction with keeping speed at a constant leakage.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830184","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV2) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (Vmin) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV2. For the first time, we have demonstrated Vmin of 1-fin F/F same as 2-fin one and 27% CV2 reduction with keeping speed at a constant leakage.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
