Jiann-Jong Chen, P. Wu, Ta-Wei Chao, Y. Ku, Yuh-Shyan Hwang, Cheng-Chieh Yu
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引用次数: 0
Abstract
In this paper, a buck converter is designed with a noise-shaping technique to reduce noise and uses synchronous rectification to increase power efficiency. The measured results show the peak noise level less than -84.5dBm at 2MHz and achieve 85% to 93.5% power efficiency with output voltage between 1.8V to 2.5V and a load current range from 50mA to 200mA. The buck converter is fabricated with TSMC 0.35μm CMOS DPQM process. The chip area is 1.417mm*1.239 mm.
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