A programmable built-in self-diagnosis for embedded SRAM

C. Selva, C. Torelli, Danilo Rimondi, Rita Zappa, S. Corbani, G. Mastrodomenico, L. Albani
{"title":"A programmable built-in self-diagnosis for embedded SRAM","authors":"C. Selva, C. Torelli, Danilo Rimondi, Rita Zappa, S. Corbani, G. Mastrodomenico, L. Albani","doi":"10.1109/MTDT.2004.4","DOIUrl":null,"url":null,"abstract":"In this work we present a built-in self-diagnosis (BISD) module, an integrated solution for the fault diagnosis of embedded memories. The BISD methodology proposed includes a built-in self-test block and an additional circuitry to perform the on-chip failure analysis in order to detect the main defects. The fault diagnosis system developed is aimed to the maturation of the technology as well as to the diagnosis of circuits in case of sudden yield drop. The fault diagnosis is a key factor for the technology maturation. New technologies require a certain time to get stability before being used for massive production. On the other hand, problems of sudden yield drop can occur also when the technology is stable. In this case a fast recovery on yield is required. This BISD module is highly re-configurable, its main characteristics are the programmability with different test algorithms, the flexibility with respect to memory sizes and address scrambling and the reconfigurability with respect to the part of the array to diagnose. The BISD block has been implemented in a 0.13 /spl mu/m flash technology with a 512Kbit SRAM, it has an area overhead of 13% and its maximum operation frequency is 150MHz.","PeriodicalId":415606,"journal":{"name":"Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2004.4","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

In this work we present a built-in self-diagnosis (BISD) module, an integrated solution for the fault diagnosis of embedded memories. The BISD methodology proposed includes a built-in self-test block and an additional circuitry to perform the on-chip failure analysis in order to detect the main defects. The fault diagnosis system developed is aimed to the maturation of the technology as well as to the diagnosis of circuits in case of sudden yield drop. The fault diagnosis is a key factor for the technology maturation. New technologies require a certain time to get stability before being used for massive production. On the other hand, problems of sudden yield drop can occur also when the technology is stable. In this case a fast recovery on yield is required. This BISD module is highly re-configurable, its main characteristics are the programmability with different test algorithms, the flexibility with respect to memory sizes and address scrambling and the reconfigurability with respect to the part of the array to diagnose. The BISD block has been implemented in a 0.13 /spl mu/m flash technology with a 512Kbit SRAM, it has an area overhead of 13% and its maximum operation frequency is 150MHz.
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嵌入式SRAM的可编程内置自诊断
在这项工作中,我们提出了一种内置自诊断(BISD)模块,一种嵌入式存储器故障诊断的集成解决方案。提出的bsd方法包括一个内置的自检模块和一个额外的电路来执行片上故障分析,以检测主要缺陷。所开发的故障诊断系统是为了使故障诊断技术日趋成熟,以及在产量突然下降的情况下对电路进行诊断。故障诊断是技术成熟的关键因素。新技术在大规模生产之前需要一定的时间来获得稳定性。另一方面,在技术稳定的情况下,也会出现产量骤降的问题。在这种情况下,需要快速恢复产量。该模块具有高度的可重构性,其主要特点是不同测试算法的可编程性、对存储器大小和地址置乱的灵活性以及对阵列部分进行诊断的可重构性。bsd块以0.13 /spl mu/m闪存技术实现,采用512Kbit SRAM,面积开销为13%,最大工作频率为150MHz。
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Built-in self-test and repair (BISTR) techniques for embedded RAMs Redundancy - it's not just for defects any more Do we need anything more than single bit error correction (ECC)? Embedded memory reliability: the SER challenge A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller
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