ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology

Abstract

ReRAMs have been demonstrated as promising next generation non-volatile memory solutions. However, they still employ high voltage, creating CMOS reliability issues. This paper discusses ReRAM device and circuit co-design in standard CMOS technology. We investigate various ReRAM device parameters such as resistance values and set/reset voltages, and ReRAM circuit operations in advanced CMOS technology. In the studied 1T1R structure, reset operation is much more critical compared to the set operation because of the larger voltage drop across the nMOS access transistor. It also determines the lower boundary of the low resistance (LRS) value. For scalable ReRAM, it is necessary to develop ReRAM technology that can scale the set/reset voltage more than the resistance.