A Low-power Low-noise Reconfigurable Bandwidth BiCMOS Neural Amplifier

Abstract

Significant advancements in miniaturized implantable electronics has given rise to a new dimension in the study of neuroscience. A low-noise neural amplifier is the first stage of an implantable electrophysiological signal recording system. This paper presents the design of a two-stage BiCMOS operational transconductance amplifier with reconfigurable bandwidth for the neural signal recording applications. The amplifier is designed using the standard 130 nm BiCMOS process. The designed amplifier achieves a closed-loop gain of 55.75 dB with a reconfigurable lower cut-off frequency of 0.13 Hz to 0.33 Hz and a higher cut-off frequency of 1.4 kHz. The reconfigurable bandwidth has been implemented by controlling the gate bias voltage of a pair of triple-well nMOS transistors working as the pseudoresistors in the feedback path. The simulated input-referred noise of the amplifier is 3.89, 3.59, 2.77 μVrms integrated over the 0.13, 0.17 and 0.33 Hz to 1 kHz frequency band respectively. The total power consumption of the amplifier is 1.5 μW with a dc-offset voltage of 12.3 mV. The designed amplifier has a CMRR (common-mode rejection ratio) and PSRR (power supply rejection ratio) of 104.8 dB and 97 dB respectively. The performance of the designed amplifier shows a good compatibility with the low-frequency neural signal recording systems.