Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620114
N. Sharma, A. Marshall, F. Register, Jin Woong Kwak
A variety of charge-based logic devices are being investigated as possible technology options for the beyond-CMOS era. The tunneling devices, such as the Bilayer Pseudo Spin Field Effect transistor (BiSFET), the Bilayer Pseudo Spin Junction Transistor (BiSJT) and the Interlayer Tunnel Field Effect Transistor (ITFET), have previously been studied for their logic capabilities. These have an intrinsic memory capability, making them an interesting candidate for standalone memory applications. The performance of these devices with respect to Complementary Metal Oxide Semiconductor (CMOS) for memory applications is presented.
{"title":"Memory Circuits using Resonant Charge-based Devices","authors":"N. Sharma, A. Marshall, F. Register, Jin Woong Kwak","doi":"10.1109/DCAS.2018.8620114","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620114","url":null,"abstract":"A variety of charge-based logic devices are being investigated as possible technology options for the beyond-CMOS era. The tunneling devices, such as the Bilayer Pseudo Spin Field Effect transistor (BiSFET), the Bilayer Pseudo Spin Junction Transistor (BiSJT) and the Interlayer Tunnel Field Effect Transistor (ITFET), have previously been studied for their logic capabilities. These have an intrinsic memory capability, making them an interesting candidate for standalone memory applications. The performance of these devices with respect to Complementary Metal Oxide Semiconductor (CMOS) for memory applications is presented.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125051465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620186
Ki Yong Kim, Heechai Kang, V. Singh, R. Gharpurey
A spectrum channelizer that employs a frequency-folded analog-to-digital converter (FF-ADC) is described. The design allows for downconversion and channelization of a broadband spectrum into contiguous sub-bands, by using polyphase downconversion, baseband analog-to-digital conversion, and sub-band separation through digital-domain harmonic rejection. The sub-bands are aliased at baseband in the polyphase paths. At baseband, the sub-bands with large signal power can reduce the effective ADC dynamic range available for those with lower power levels. An approach that employs pulse-width-modulated local oscillator (PWM-LO) waveforms in the polyphase paths, for equalizing the sub-bands at baseband, prior to digitization, is proposed to address this issue. The approach makes it possible to vary the spectral response of the FF-ADC with low signal-path complexity.
{"title":"A Broadband Spectrum Channelizer with PWM-LO Based Sub-Band Equalization","authors":"Ki Yong Kim, Heechai Kang, V. Singh, R. Gharpurey","doi":"10.1109/DCAS.2018.8620186","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620186","url":null,"abstract":"A spectrum channelizer that employs a frequency-folded analog-to-digital converter (FF-ADC) is described. The design allows for downconversion and channelization of a broadband spectrum into contiguous sub-bands, by using polyphase downconversion, baseband analog-to-digital conversion, and sub-band separation through digital-domain harmonic rejection. The sub-bands are aliased at baseband in the polyphase paths. At baseband, the sub-bands with large signal power can reduce the effective ADC dynamic range available for those with lower power levels. An approach that employs pulse-width-modulated local oscillator (PWM-LO) waveforms in the polyphase paths, for equalizing the sub-bands at baseband, prior to digitization, is proposed to address this issue. The approach makes it possible to vary the spectral response of the FF-ADC with low signal-path complexity.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123551830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620116
Jiong Si, Sarah L. Harris, E. Yfantis
In this paper we propose a dynamic Rectified Linear Unit (D-ReLU) activation function for a multi-layer perceptron (MLP) learning network. We also implement the forward propagation of 2- and 3-layer multi-layer perceptron (MLP) networks with this D-ReLU function on a Cyclone IVE field programmable gate array (FPGA) using 8-bit precision. When compared to networks that use the approximated Sigmoid activation function, our proposed D-ReLU function uses 18-23% less area with only a 0.7-2.9% loss in accuracy. Moreover, the simplified calculations of the D-ReLU function result in 14% and 57% decreases in software execution time than Sigmoid function. In the FPGA hardware implementation, the D-ReLU function uses two fewer clock cycles per layer than the approximated Sigmoid activation function. Thus, using the D-ReLU activation function in MLP networks results in reduced area on an FPGA and lower execution time in software. In addition, the FPGA implementation runs at a 60× lower clock rate than the software version with a 29× faster execution time, indicating a potential of over 1,700× power savings.
{"title":"A Dynamic ReLU on Neural Network","authors":"Jiong Si, Sarah L. Harris, E. Yfantis","doi":"10.1109/DCAS.2018.8620116","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620116","url":null,"abstract":"In this paper we propose a dynamic Rectified Linear Unit (D-ReLU) activation function for a multi-layer perceptron (MLP) learning network. We also implement the forward propagation of 2- and 3-layer multi-layer perceptron (MLP) networks with this D-ReLU function on a Cyclone IVE field programmable gate array (FPGA) using 8-bit precision. When compared to networks that use the approximated Sigmoid activation function, our proposed D-ReLU function uses 18-23% less area with only a 0.7-2.9% loss in accuracy. Moreover, the simplified calculations of the D-ReLU function result in 14% and 57% decreases in software execution time than Sigmoid function. In the FPGA hardware implementation, the D-ReLU function uses two fewer clock cycles per layer than the approximated Sigmoid activation function. Thus, using the D-ReLU activation function in MLP networks results in reduced area on an FPGA and lower execution time in software. In addition, the FPGA implementation runs at a 60× lower clock rate than the software version with a 29× faster execution time, indicating a potential of over 1,700× power savings.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131201029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620180
M. Chilukuri, Sungyong Jung
A mixed mode variable gain amplifier for hearing aid application is presented. It consists of main amplifier stage and a gain control circuit. Based on the output of microphone, voltage levels are categorized into two gain regions and designed circuit automatically sets the close loop gain of main amplifier. Main amplifier consists of opamp with feedback resistors and gain control circuit consists of peak detector, high speed comparator and XNOR gate. Due to high speed digital control circuitry, attack and release time are as small as 60µSec which is 33 times faster than temporal resolution of human hearing. Along with preamplifier, proposed circuit achieves a gain range of 45dB to 65dB and offers an input referred noise of 0.13µVrms, with peak SNR of 77dB and consumes a power of 172µW from 1.8V supply. Circuit is designed in 0.18µm CMOS process and occupies an area of 493µm × 184µm.
{"title":"A Mixed-Mode Variable Gain Amplifier for Hearing Aid Devices","authors":"M. Chilukuri, Sungyong Jung","doi":"10.1109/DCAS.2018.8620180","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620180","url":null,"abstract":"A mixed mode variable gain amplifier for hearing aid application is presented. It consists of main amplifier stage and a gain control circuit. Based on the output of microphone, voltage levels are categorized into two gain regions and designed circuit automatically sets the close loop gain of main amplifier. Main amplifier consists of opamp with feedback resistors and gain control circuit consists of peak detector, high speed comparator and XNOR gate. Due to high speed digital control circuitry, attack and release time are as small as 60µSec which is 33 times faster than temporal resolution of human hearing. Along with preamplifier, proposed circuit achieves a gain range of 45dB to 65dB and offers an input referred noise of 0.13µVrms, with peak SNR of 77dB and consumes a power of 172µW from 1.8V supply. Circuit is designed in 0.18µm CMOS process and occupies an area of 493µm × 184µm.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130168763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620179
Sen Li, B. Fahimi
This paper presents a low-cost, inductor-free Chua’s circuit which incorporates high linearity voltage-controlled resistor (VCR). Compared with the conventional circuit topology with fixed physical inductor, the inductor-free version offers extra degree of flexibility in setting the desired inductance value, and facilitates the measurement and monitoring of the virtual inductor current. Apart from these benefits, one major advantage of the proposed circuit lies in convenient generation of experimental bifurcation diagram using VCR, which provides one with panoramic view of circuit behavior under certain parametric variation. The analytical model and circuit configuration are briefly discussed, and experimental study is conducted to confirm the practicality of the proposed circuit topology.
{"title":"Inductor-free Chua’s Circuit Employing Linear Voltage-controlled Resistor","authors":"Sen Li, B. Fahimi","doi":"10.1109/DCAS.2018.8620179","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620179","url":null,"abstract":"This paper presents a low-cost, inductor-free Chua’s circuit which incorporates high linearity voltage-controlled resistor (VCR). Compared with the conventional circuit topology with fixed physical inductor, the inductor-free version offers extra degree of flexibility in setting the desired inductance value, and facilitates the measurement and monitoring of the virtual inductor current. Apart from these benefits, one major advantage of the proposed circuit lies in convenient generation of experimental bifurcation diagram using VCR, which provides one with panoramic view of circuit behavior under certain parametric variation. The analytical model and circuit configuration are briefly discussed, and experimental study is conducted to confirm the practicality of the proposed circuit topology.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126973229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620183
Shaghayegh Aslanzadeh, A. Hedayatipour, Mst Shamim Ara Shawkat, N. Mcfarlane
Over the past few years, ion-sensitive field-effect transistors (ISFETs) have played a major role in chemical detection systems. This paper presents an architecture for an ultra-low power CMOS pH sensor suitable for biomedical applications. The design uses a differential ISFET readout circuit operating at 0.9V power supply. The minimum supply voltage and minimum power consumption are achieved by operating the MOSFETs in subthreshold regions. The novelty of this design lies in using different size sensing gate areas in a differential voltage clamping ISFET topology. The ISFET model is derived from experimental measurements. Simulation results of the circuit in a 0.5µm standard CMOS process show that the designed differential ISFET provides an average sensitivity −49mV/pH with ISFET sensing areas of 80µm×80µm and 10µm×10µm over a 1-14pH range with 2.3nW of power.
{"title":"A Differential Low-Power Voltage-Clamped ISFET Topology for Biomedical Applications","authors":"Shaghayegh Aslanzadeh, A. Hedayatipour, Mst Shamim Ara Shawkat, N. Mcfarlane","doi":"10.1109/DCAS.2018.8620183","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620183","url":null,"abstract":"Over the past few years, ion-sensitive field-effect transistors (ISFETs) have played a major role in chemical detection systems. This paper presents an architecture for an ultra-low power CMOS pH sensor suitable for biomedical applications. The design uses a differential ISFET readout circuit operating at 0.9V power supply. The minimum supply voltage and minimum power consumption are achieved by operating the MOSFETs in subthreshold regions. The novelty of this design lies in using different size sensing gate areas in a differential voltage clamping ISFET topology. The ISFET model is derived from experimental measurements. Simulation results of the circuit in a 0.5µm standard CMOS process show that the designed differential ISFET provides an average sensitivity −49mV/pH with ISFET sensing areas of 80µm×80µm and 10µm×10µm over a 1-14pH range with 2.3nW of power.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114274400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620112
Masoud Shahshahani, Pingakshya Goswami, D. Bhatia
Deep Learning has played an important role in the classification of images, speech recognition, and natural language processing. Traditionally, these learning algorithms are implemented in clusters of CPUs and GPUs. But with the increase in data size, the models created on CPUs and GPUs are not scalable. Hence we need a hardware model which can be scaled beyond current data and model sizes. This is where FPGA comes into place. With the advancement of CAD tools for FPGAs, the designers do not need to create the architectures of the networks in RTL level using HDLs like Verilog and VHDL. They can use High-level Language like C or C++ to build the models using tools like Xilinx Vivado HLS. Also, the power consumption of FPGA based models for deep learning is substantially low as compared to GPUs. In this paper, we have done an extensive survey of various implementations of FPGA based deep learning architectures with emphasis on Convolutional Neural Networks (CNN). The CNN architectures presented in the literature consume large memory for the storage of weights and images. It is not possible to store this information in the internal FPGA Block RAM. This paper presents comprehensive servery of the methods and techniques used in literatures to tackle the memory consumption issue and how the data movement between high storage external DDR memory and internal BRAM can be reduced.
{"title":"Memory Optimization Techniques for FPGA based CNN Implementations","authors":"Masoud Shahshahani, Pingakshya Goswami, D. Bhatia","doi":"10.1109/DCAS.2018.8620112","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620112","url":null,"abstract":"Deep Learning has played an important role in the classification of images, speech recognition, and natural language processing. Traditionally, these learning algorithms are implemented in clusters of CPUs and GPUs. But with the increase in data size, the models created on CPUs and GPUs are not scalable. Hence we need a hardware model which can be scaled beyond current data and model sizes. This is where FPGA comes into place. With the advancement of CAD tools for FPGAs, the designers do not need to create the architectures of the networks in RTL level using HDLs like Verilog and VHDL. They can use High-level Language like C or C++ to build the models using tools like Xilinx Vivado HLS. Also, the power consumption of FPGA based models for deep learning is substantially low as compared to GPUs. In this paper, we have done an extensive survey of various implementations of FPGA based deep learning architectures with emphasis on Convolutional Neural Networks (CNN). The CNN architectures presented in the literature consume large memory for the storage of weights and images. It is not possible to store this information in the internal FPGA Block RAM. This paper presents comprehensive servery of the methods and techniques used in literatures to tackle the memory consumption issue and how the data movement between high storage external DDR memory and internal BRAM can be reduced.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114729699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620187
Md. Sakib Hasan, Catherine D. Schuman, J. Najem, Ryan Weiss, Nicholas D. Skuda, A. Belianinov, C. Collier, Stephen A. Sarles, G. Rose
Neuromorphic computing refers to a variety of brain-inspired computers, devices, and models inspired by the interconnectivity, performance, and energy efficiency of the human brain. Unlike the ubiquitous von Neumann computer architectures with complex processor cores and sequential computation, biological neurons and synapses operate by storing and processing information simultaneously with the capacity of flexible adaptation resulting in massive computational capability with much less power consumption. The search for a synaptic material which can closely imitate bio-synapse has led to an alamethicin-doped, synthetic biomembrane which can emulate key synaptic functions due to generic memristive property enabling learning and computation. This two-terminal, biomolecular memristor, in contrast to its solid-state counterparts, features similar structure, switching mechanism, and ionic transport modality as biological synapses while consuming considerably lower power. In this paper, we outline a methodology for using this biomolecular synapse to build neural networks capable of solving real-world problems. The physical mechanism underlying its volatile memristance is explored followed by the development of a model of this device for circuit simulation. We outline a circuit design technique to integrate this synapse with solid-state neuron circuit for hardware implementation. Based on these results, we develop a high level simulation framework and use a training scheme called Evolutionary Optimization for Neuromorphic System (EONS) to generate networks for solving two problems, namely iris dataset classification and EEG classification task. The small network size and comparable to state-of-the-art accuracy of these preliminary networks show its potential to enhance synaptic functionality in next generation neuromorphic hardware.
{"title":"Biomimetic, Soft-Material Synapse for Neuromorphic Computing: from Device to Network","authors":"Md. Sakib Hasan, Catherine D. Schuman, J. Najem, Ryan Weiss, Nicholas D. Skuda, A. Belianinov, C. Collier, Stephen A. Sarles, G. Rose","doi":"10.1109/DCAS.2018.8620187","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620187","url":null,"abstract":"Neuromorphic computing refers to a variety of brain-inspired computers, devices, and models inspired by the interconnectivity, performance, and energy efficiency of the human brain. Unlike the ubiquitous von Neumann computer architectures with complex processor cores and sequential computation, biological neurons and synapses operate by storing and processing information simultaneously with the capacity of flexible adaptation resulting in massive computational capability with much less power consumption. The search for a synaptic material which can closely imitate bio-synapse has led to an alamethicin-doped, synthetic biomembrane which can emulate key synaptic functions due to generic memristive property enabling learning and computation. This two-terminal, biomolecular memristor, in contrast to its solid-state counterparts, features similar structure, switching mechanism, and ionic transport modality as biological synapses while consuming considerably lower power. In this paper, we outline a methodology for using this biomolecular synapse to build neural networks capable of solving real-world problems. The physical mechanism underlying its volatile memristance is explored followed by the development of a model of this device for circuit simulation. We outline a circuit design technique to integrate this synapse with solid-state neuron circuit for hardware implementation. Based on these results, we develop a high level simulation framework and use a training scheme called Evolutionary Optimization for Neuromorphic System (EONS) to generate networks for solving two problems, namely iris dataset classification and EEG classification task. The small network size and comparable to state-of-the-art accuracy of these preliminary networks show its potential to enhance synaptic functionality in next generation neuromorphic hardware.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122526954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620111
H. Wei, M. Laszewski, N. Kehtarnavaz
This paper presents a deep learning-based approach to detect and classify persons in video data captured from distances of several miles via a high-power lens video camera. For detection, a set of computationally efficient image processing steps are considered to identify moving areas that contain a person. These areas are then passed onto a convolutional neural network classifier whose convolutional layers consist of the GoogleNet transfer learning. Despite the challenges associated with the video dataset examined in terms of the low resolution of persons appearing in the video data and the presence of heat haze and camera shaking, the developed approach generated 90% classification accuracy.
{"title":"Deep Learning-Based Person Detection and Classification for Far Field Video Surveillance","authors":"H. Wei, M. Laszewski, N. Kehtarnavaz","doi":"10.1109/DCAS.2018.8620111","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620111","url":null,"abstract":"This paper presents a deep learning-based approach to detect and classify persons in video data captured from distances of several miles via a high-power lens video camera. For detection, a set of computationally efficient image processing steps are considered to identify moving areas that contain a person. These areas are then passed onto a convolutional neural network classifier whose convolutional layers consist of the GoogleNet transfer learning. Despite the challenges associated with the video dataset examined in terms of the low resolution of persons appearing in the video data and the presence of heat haze and camera shaking, the developed approach generated 90% classification accuracy.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127105477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620178
Sameer Arora, P. Balsara, D. Bhatia, P. Buck
The proposed gain and phase (GAP) measurement architecture is a digitally-implemented device, which is used to measure the gain and phase of DC-DC voltage converters. The device excites the system under test with a small-signal sinusoidal test signal and measures both the time histories of the test signal and the response signal. The device sweeps different frequency points using the direct-digital-synthesis (DDS) technique. Further, to achieve a wide dynamic range, the phase and amplitude response (Bode plot) are calculated using the Lock-in amplifier technique. The device has the flexibility of sampling the response in either the off-time, the on-time or at any other time (average) sampling of the power switch for the DC-DC converter. Furthermore, the proposed system is integrated with a graphical user interface (GUI) which communicates with the device. Through the GUI the user may select to perform measurements such as the transfer function of the plant, the open loop and the closed loop of the controller, measurement of audio susceptibility, total harmonic distortion and noise (THD+N) and ripple spectrum. The GUI can also be used to design a Pulse Width Modulation (PWM) linear controller on the fly, estimating the open loop response T(s), the closed loop response T(s)/(1+T(s)) and the inverse loop response 1/T(s). Analysis of the proposed system is provided, alongside with various applications and experimental results.
{"title":"A Novel Digital Architecture for Gain and Phase Measurements for DC-DC Converters","authors":"Sameer Arora, P. Balsara, D. Bhatia, P. Buck","doi":"10.1109/DCAS.2018.8620178","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620178","url":null,"abstract":"The proposed gain and phase (GAP) measurement architecture is a digitally-implemented device, which is used to measure the gain and phase of DC-DC voltage converters. The device excites the system under test with a small-signal sinusoidal test signal and measures both the time histories of the test signal and the response signal. The device sweeps different frequency points using the direct-digital-synthesis (DDS) technique. Further, to achieve a wide dynamic range, the phase and amplitude response (Bode plot) are calculated using the Lock-in amplifier technique. The device has the flexibility of sampling the response in either the off-time, the on-time or at any other time (average) sampling of the power switch for the DC-DC converter. Furthermore, the proposed system is integrated with a graphical user interface (GUI) which communicates with the device. Through the GUI the user may select to perform measurements such as the transfer function of the plant, the open loop and the closed loop of the controller, measurement of audio susceptibility, total harmonic distortion and noise (THD+N) and ripple spectrum. The GUI can also be used to design a Pulse Width Modulation (PWM) linear controller on the fly, estimating the open loop response T(s), the closed loop response T(s)/(1+T(s)) and the inverse loop response 1/T(s). Analysis of the proposed system is provided, alongside with various applications and experimental results.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"194-199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：