Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times

S. Srivastava, J. Roychowdhury
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引用次数: 8

Abstract

Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(tau) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS latch/register structures, obtaining speedups of 4-10times over the current standard of binary search
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通过设置/保持时间的直接牛顿解快速准确的锁存表征
表征锁存器和寄存器的设置/保持时间是实现大型数字设计定时关闭的关键组件,在英特尔和IBM等行业通常需要花费数月的计算时间。我们提出了一种加速闩锁表征的新方法,该方法将设置/保持时间问题表述为使用状态转移函数导出的标量非线性方程h(tau) = 0,然后用牛顿-拉夫森(NR)求解该方程。NR的局部二次收敛导致每次迭代精度的快速提高,从而显着减少准确确定设置/保持时间所需的计算。我们在传输门和C2MOS锁存/寄存器结构上验证了新方法的快速收敛和计算优势,获得了比当前标准二进制搜索快4-10倍的速度
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