Configurable hardware implementation of a pipelined DNLMS adaptive filter

Abstract

The delayed normalized least-mean-square (DNLMS) adaptive filtering algorithm is suitable for implementing pipelined architectures. Though previous literature has provided such architectures for DNLMS adaptive filters, none have given a detailed implementation. This paper presents the configurable hardware implementation of a pipelined, modular, low-latency, portable DNLMS adaptive filter which is tested for echo cancellation. The design is implemented onto the Altera Stratix FPGA and has a maximum operating frequency of 32.27 MHz. The design methodology consists of architectural derivation, fixed-point and RTL simulations, physical synthesis, and real-time hardware.