T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka
{"title":"3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS","authors":"T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka","doi":"10.1109/S3S.2013.6716513","DOIUrl":null,"url":null,"abstract":"InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2013.6716513","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
