{"title":"Opposite side floating gate SOI FLASH memory cell","authors":"Xinnan Lin, M. Chan, Hongmei Wang","doi":"10.1109/HKEDM.2000.904205","DOIUrl":null,"url":null,"abstract":"An opposite side floating gate SOI FLASH memory cell has been proposed for advanced device scaling. The new structure has the read gate and floating gate on the opposite sides of the active silicon film. It allows the use of a thick tunneling oxide to prevent charge leakage and a thin gate oxide for device scaling. The functionality of the device is demonstrated through the analysis of threshold voltage shift before and after programming. The effects of various parameters such as front and back gate oxide thickness, silicon film thickness and channel doping on device performance have been studied and a possible way to fabricate the device is proposed.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HKEDM.2000.904205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
An opposite side floating gate SOI FLASH memory cell has been proposed for advanced device scaling. The new structure has the read gate and floating gate on the opposite sides of the active silicon film. It allows the use of a thick tunneling oxide to prevent charge leakage and a thin gate oxide for device scaling. The functionality of the device is demonstrated through the analysis of threshold voltage shift before and after programming. The effects of various parameters such as front and back gate oxide thickness, silicon film thickness and channel doping on device performance have been studied and a possible way to fabricate the device is proposed.