Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers

Abstract

This paper for the first time successfully demonstrates a Logic-compatible, highly reliable, automotive-grade 16Mb flash macro with self- aligned, split-gate FG-based flash cell embedded into a 40nm Low Power CMOS with copper low-K interconnects. Key Features of the flash macro: Dual power supply with operation temperature from -40 to 150oC; Random Read access 10ns @ worst case condition; Low active and standby power; High raw endurance and data retention lifetime before using ECC. This technology provides large read current window which is compatible with both automotive MCU markets and low power mode tailored for smart card/industrial applications. The 16Mb Design test chip (DTC) with industry-leading cell size has demonstrated functionality with tight cell Vt and read current distributions. The SG NVM cell and erase gate are processed with self-alignment to gate spacer and polysilicon CMP (Chemical Mechanical Polishing) that can be easily integrated in a modular way to the standard logic process.