Pub Date : 2016-06-23DOI: 10.1109/IMW.2016.7495284
G. Navarro, V. Sousa, P. Noé, N. Castellani, M. Coue, J. Kluge, A. Kiouseloglou, C. Sabbione, A. Persico, A. Roule, O. Cueto, S. Blonkowski, F. Fillot, N. Bernier, R. Annunziata, M. Borghi, E. Palumbo, P. Zuliani, L. Perniola
In this paper we investigate the impact of N- doping in optimized Ge-rich Ge2Sb2Te5 materials on device programming and storing performance. We integrate these alloys in state-of-the-art Phase- Change Memory (PCM) cells and we analyze the efficiency of the SET operation in N-doped and undoped memory cells, comparing voltage based programming with current based programming. This aspect is extensively investigated through electrical characterization, physico-chemical analysis and electro-thermal simulations. The thermal stability of these devices is finally evaluated and high temperature data retention is granted enabling PCM for embedded applications.
{"title":"N-Doping Impact in Optimized Ge-Rich Materials Based Phase-Change Memory","authors":"G. Navarro, V. Sousa, P. Noé, N. Castellani, M. Coue, J. Kluge, A. Kiouseloglou, C. Sabbione, A. Persico, A. Roule, O. Cueto, S. Blonkowski, F. Fillot, N. Bernier, R. Annunziata, M. Borghi, E. Palumbo, P. Zuliani, L. Perniola","doi":"10.1109/IMW.2016.7495284","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495284","url":null,"abstract":"In this paper we investigate the impact of N- doping in optimized Ge-rich Ge2Sb2Te5 materials on device programming and storing performance. We integrate these alloys in state-of-the-art Phase- Change Memory (PCM) cells and we analyze the efficiency of the SET operation in N-doped and undoped memory cells, comparing voltage based programming with current based programming. This aspect is extensively investigated through electrical characterization, physico-chemical analysis and electro-thermal simulations. The thermal stability of these devices is finally evaluated and high temperature data retention is granted enabling PCM for embedded applications.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115149922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7495276
A.Sai Kumar, M. Sarkar, M. Suri
This paper presents a first of its kind unique application of OxRAM devices in CMOS image sensor pixels. Our proposed hybrid CMOS-OxRAM pixel circuit exploits the non-linear capacitive and resistive properties of OxRAM device to control image overexposure autonomously. HfOx based OxRAM device is used as a programmable capacitive load in a conventional 4T-APS (active pixel sensor) circuit. Our solution exploiting HfOx based OxRAM devices, improves the dynamic range of individual pixels by a factor of ~2.45 (or 7.8 dB), and capacitance density by a factor of ~5 at 180 nm node.
{"title":"Hybrid CMOS-OxRAM Image Sensor for Overexposure Control","authors":"A.Sai Kumar, M. Sarkar, M. Suri","doi":"10.1109/IMW.2016.7495276","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495276","url":null,"abstract":"This paper presents a first of its kind unique application of OxRAM devices in CMOS image sensor pixels. Our proposed hybrid CMOS-OxRAM pixel circuit exploits the non-linear capacitive and resistive properties of OxRAM device to control image overexposure autonomously. HfOx based OxRAM device is used as a programmable capacitive load in a conventional 4T-APS (active pixel sensor) circuit. Our solution exploiting HfOx based OxRAM devices, improves the dynamic range of individual pixels by a factor of ~2.45 (or 7.8 dB), and capacitance density by a factor of ~5 at 180 nm node.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117214367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7495292
H. Lue, P. Du, R. Lo, Chih-Yuan Lu
The planar flat FG device is theoretically studied extensively. There is a puzzle whether the charge is stored in the inter gate dielectric (IGD). A planar cell has no geometrical coupling ratio help thus IGD bears very high E-field. A high work function FG together with a robust interfacial layer between FG and high-K material that has both large barrier height and large dielectric constant are needed to reduce the out tunneling current. Thus our detailed tunneling simulation indicates that to obtain an “ideal planar FG” device with a large memory window but without charge-trapping in IGD is quite challenging. On the other hand, a very interesting finding from our simulation is that the opposite scenario assuming charge trapping in IGD can also provide identical ISPP/ISPE characteristic as the ideal FG device. This leads to a paradox (Rashomon) for a correct theoretical model for the device. In order to solve this paradox, we propose to apply a gate-sensing and channel-sensing (GSCS) technique to detect the charge location and dig out the real answer of operation principle. GSCS study of FG SONOS “Fusion” device shows that in a device that has both FG and trapping IGD the FG holds only limited amount of electrons and most electrons are stored in the IGD. Finally, the FG/CT fusion devices of the planar FG SONOS and FG BE-SONOS (without high-K and metal gate) are experimentally studied. They show very large memory window (>16V) with nearly ideal ISPP/ISPE slope ~1.
{"title":"Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle","authors":"H. Lue, P. Du, R. Lo, Chih-Yuan Lu","doi":"10.1109/IMW.2016.7495292","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495292","url":null,"abstract":"The planar flat FG device is theoretically studied extensively. There is a puzzle whether the charge is stored in the inter gate dielectric (IGD). A planar cell has no geometrical coupling ratio help thus IGD bears very high E-field. A high work function FG together with a robust interfacial layer between FG and high-K material that has both large barrier height and large dielectric constant are needed to reduce the out tunneling current. Thus our detailed tunneling simulation indicates that to obtain an “ideal planar FG” device with a large memory window but without charge-trapping in IGD is quite challenging. On the other hand, a very interesting finding from our simulation is that the opposite scenario assuming charge trapping in IGD can also provide identical ISPP/ISPE characteristic as the ideal FG device. This leads to a paradox (Rashomon) for a correct theoretical model for the device. In order to solve this paradox, we propose to apply a gate-sensing and channel-sensing (GSCS) technique to detect the charge location and dig out the real answer of operation principle. GSCS study of FG SONOS “Fusion” device shows that in a device that has both FG and trapping IGD the FG holds only limited amount of electrons and most electrons are stored in the IGD. Finally, the FG/CT fusion devices of the planar FG SONOS and FG BE-SONOS (without high-K and metal gate) are experimentally studied. They show very large memory window (>16V) with nearly ideal ISPP/ISPE slope ~1.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124718080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7493571
Jens Spinner, Mohammed Rajab, J. Freudenberger
This work proposes a construction for high-rate generalized concatenated (GC) codes. The proposed codes are well suited for error correction in flash memories for high reliability data storage. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. For the inner codes we propose extended BCH codes, where we apply single parity-check codes in the first level of the GC code. This enables high-rate codes.
{"title":"Construction of High-Rate Generalized Concatenated Codes for Applications in Non-Volatile Flash Memories","authors":"Jens Spinner, Mohammed Rajab, J. Freudenberger","doi":"10.1109/IMW.2016.7493571","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493571","url":null,"abstract":"This work proposes a construction for high-rate generalized concatenated (GC) codes. The proposed codes are well suited for error correction in flash memories for high reliability data storage. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. For the inner codes we propose extended BCH codes, where we apply single parity-check codes in the first level of the GC code. This enables high-rate codes.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126262710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7495296
G. Piccolboni, M. Parise, G. Molas, A. Levisse, J. Portal, R. Coquand, C. Carabasse, M. Bernard, A. Roule, J. Noel, B. Giraud, M. Harrand, C. Cagli, T. Magis, E. Vianello, B. De Salvo, G. Ghibaudo, L. Perniola
In this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then 2 potential applications are discussed using design approach. For high density, the Vertical RRAM cell features and circuit are dimensioned to optimize the memory page density. Finally, for neuromorphic applications, selector and array configuration are tuned to reduce the variability in terms of voltage seen by each cell constituting a vertical synapse.
{"title":"Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives","authors":"G. Piccolboni, M. Parise, G. Molas, A. Levisse, J. Portal, R. Coquand, C. Carabasse, M. Bernard, A. Roule, J. Noel, B. Giraud, M. Harrand, C. Cagli, T. Magis, E. Vianello, B. De Salvo, G. Ghibaudo, L. Perniola","doi":"10.1109/IMW.2016.7495296","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495296","url":null,"abstract":"In this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then 2 potential applications are discussed using design approach. For high density, the Vertical RRAM cell features and circuit are dimensioned to optimize the memory page density. Finally, for neuromorphic applications, selector and array configuration are tuned to reduce the variability in terms of voltage seen by each cell constituting a vertical synapse.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130938701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7493561
Tsukasa Tokutomi, K. Takeuchi
Highly reliable LDPC ECC is introduced to improve the reliability of solid-state drives (SSDs). Although conventional AEP-LDPC ECC [3] is 12x highly reliable than BCH ECC, its error-correction capability is degraded due to the burst-errors and inaccurate log- likelihood ratio (LLR). To improve the reliability of TLC NAND flash, this paper proposes the burst-error masking (BEM) and program-disturb merged LLR estimation (PMLE). The first proposal, BEM eliminates the burst- errors by recording the error-location to the table. The second proposal, PMLE calculates the ratio of program-disturb errors to data-retention errors. As a result, more precise LLR is obtained. By combining BEM and PMLE, the SSD lifetime is extended by 17x and the table size overhead is reduced by 81%.
{"title":"17x Reliability Enhanced LDPC Code with Burst-Error Masking and High-Precision LLR for Highly Reliable Solid-State-Drives with TLC NAND Flash Memory","authors":"Tsukasa Tokutomi, K. Takeuchi","doi":"10.1109/IMW.2016.7493561","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493561","url":null,"abstract":"Highly reliable LDPC ECC is introduced to improve the reliability of solid-state drives (SSDs). Although conventional AEP-LDPC ECC [3] is 12x highly reliable than BCH ECC, its error-correction capability is degraded due to the burst-errors and inaccurate log- likelihood ratio (LLR). To improve the reliability of TLC NAND flash, this paper proposes the burst-error masking (BEM) and program-disturb merged LLR estimation (PMLE). The first proposal, BEM eliminates the burst- errors by recording the error-location to the table. The second proposal, PMLE calculates the ratio of program-disturb errors to data-retention errors. As a result, more precise LLR is obtained. By combining BEM and PMLE, the SSD lifetime is extended by 17x and the table size overhead is reduced by 81%.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126735585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7495268
M. Azzaz, E. Vianello, B. Sklénard, P. Blaise, A. Roule, C. Sabbione, S. Bernasconi, C. Charpin, C. Cagli, E. Jalaguier, S. Jeannot, S. Denorme, P. Candelier, M. Yu, L. Nistor, C. Fenouillet-Béranger, L. Perniola
In this paper the memory performances of the TiN/HfO2/Ti/TiN and TiN/Ta2O5/TaOx/TiN memory stacks are compared. First, the bipolar switching parameters and the effect of the compliance current on the memory window and endurance are investigated. Then, the endurance and data retention properties are compared at a given operating current (100μA). Ta2O5 based memory stack exhibits a better memory window (2 decades) and data retention, while the HfO2 one shows good endurance properties (108 cycles). Finally, thanks to ab initio calculations using Density Functional Theory, the stability of the conductive filament is investigated in both HfOx and TaOx dielectrics.
{"title":"Endurance/Retention Trade Off in HfOx and TaOx Based RRAM","authors":"M. Azzaz, E. Vianello, B. Sklénard, P. Blaise, A. Roule, C. Sabbione, S. Bernasconi, C. Charpin, C. Cagli, E. Jalaguier, S. Jeannot, S. Denorme, P. Candelier, M. Yu, L. Nistor, C. Fenouillet-Béranger, L. Perniola","doi":"10.1109/IMW.2016.7495268","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495268","url":null,"abstract":"In this paper the memory performances of the TiN/HfO<sub>2</sub>/Ti/TiN and TiN/Ta<sub>2</sub>O<sub>5</sub>/TaOx/TiN memory stacks are compared. First, the bipolar switching parameters and the effect of the compliance current on the memory window and endurance are investigated. Then, the endurance and data retention properties are compared at a given operating current (100μA). Ta<sub>2</sub>O<sub>5</sub> based memory stack exhibits a better memory window (2 decades) and data retention, while the HfO<sub>2</sub> one shows good endurance properties (10<sup>8</sup> cycles). Finally, thanks to ab initio calculations using Density Functional Theory, the stability of the conductive filament is investigated in both HfO<sub>x</sub> and TaO<sub>x</sub> dielectrics.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126658319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7495275
Yong Kyu Lee, Hongkook Min, Changmin Jeon, B. Seo, Gayoung Lee, Eunkang Park, Donghyun Kim, Changhyun Park, B. Kwon, Minsu Kim, Bongsang Lee, Duckhyung Lee, Hyosang Lee, Jisung Kim, Sunghee Cho
We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns random access time, 25us write time and less than 2ms erase operation) and robust reliability (1M cycle, 20 retention) are achieved. It has been successfully verified in range of 1Mb up to 16Mb density flash IPs.
{"title":"Highly Scalable 2nd-Generation 45-nm Split-Gate Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance","authors":"Yong Kyu Lee, Hongkook Min, Changmin Jeon, B. Seo, Gayoung Lee, Eunkang Park, Donghyun Kim, Changhyun Park, B. Kwon, Minsu Kim, Bongsang Lee, Duckhyung Lee, Hyosang Lee, Jisung Kim, Sunghee Cho","doi":"10.1109/IMW.2016.7495275","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495275","url":null,"abstract":"We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns random access time, 25us write time and less than 2ms erase operation) and robust reliability (1M cycle, 20 retention) are achieved. It has been successfully verified in range of 1Mb up to 16Mb density flash IPs.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124978481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7493568
Y. Yamaga, C. Matsui, Shogo Hachiya, K. Takeuchi
The performance of NAND flash based solid-state drives (SSDs) is highly dependent on the application's read and write characteristics [3], where "intensity" is defined as ratio of read:write requests, and "write- hot/cold" considers the write frequency. Moreover, NAND flash memory's reliability degrades with write/erase (W/E) cycling. To optimize performance and reliability, conventional error-correcting code (ECC) scheme switches from fast conventional Bose-Chaudhuri- Hocquenghem (BCH) to slower conventional Low Density Parity Check (LDPC), when the page error rate exceeds BCH's decoding capability. However, advanced LDPCs have been reported, called Quick-LDPC [8] and Error- Prediction (EP-) LDPC without (w/o) upper/lower cells [8], which have (i) higher error correction capability compared to conventional BCH and (ii) shorter decoding time than conventional soft-decoding LDPC. Therefore, this paper proposes an application optimized adaptive (AOA-) ECC for Multi-Level-Cell (MLC) NAND flash-based enterprise SSDs. AOA-ECC includes a new algorithm to efficiently combine the two advanced LDPCs, considering the application's characteristics and memory's W/E cycles. A firmware in the proposed SSD system chooses the optimal advanced LDPC, based on whether the application is read/write-intensive and/or write- hot/cold. Using the proposed AOA-ECC SSD with MLC NAND flash, performance improves by up to 3-times, the reliability improves by 57% and the ECC decoder area decreases by 25%.
{"title":"Application Optimized Adaptive ECC with Advanced LDPCs to Resolve Trade-Off among Reliability, Performance, and Cost of Solid-State Drives","authors":"Y. Yamaga, C. Matsui, Shogo Hachiya, K. Takeuchi","doi":"10.1109/IMW.2016.7493568","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493568","url":null,"abstract":"The performance of NAND flash based solid-state drives (SSDs) is highly dependent on the application's read and write characteristics [3], where \"intensity\" is defined as ratio of read:write requests, and \"write- hot/cold\" considers the write frequency. Moreover, NAND flash memory's reliability degrades with write/erase (W/E) cycling. To optimize performance and reliability, conventional error-correcting code (ECC) scheme switches from fast conventional Bose-Chaudhuri- Hocquenghem (BCH) to slower conventional Low Density Parity Check (LDPC), when the page error rate exceeds BCH's decoding capability. However, advanced LDPCs have been reported, called Quick-LDPC [8] and Error- Prediction (EP-) LDPC without (w/o) upper/lower cells [8], which have (i) higher error correction capability compared to conventional BCH and (ii) shorter decoding time than conventional soft-decoding LDPC. Therefore, this paper proposes an application optimized adaptive (AOA-) ECC for Multi-Level-Cell (MLC) NAND flash-based enterprise SSDs. AOA-ECC includes a new algorithm to efficiently combine the two advanced LDPCs, considering the application's characteristics and memory's W/E cycles. A firmware in the proposed SSD system chooses the optimal advanced LDPC, based on whether the application is read/write-intensive and/or write- hot/cold. Using the proposed AOA-ECC SSD with MLC NAND flash, performance improves by up to 3-times, the reliability improves by 57% and the ECC decoder area decreases by 25%.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-15DOI: 10.1109/IMW.2016.7493562
S. Lai, H. Lue, T. Hsu, C. Wu, Li-yang Liang, P. Du, C. Chiu, Chih-Yuan Lu
Vertical channel (VC) 3D NAND Flash may be categorized into two types of channel formation: (1) "U-turn" string, where both BL and source are connected at top thus channel current flows in a U-turn way; (2) "Bottom source", where source is connected at the bottom thus channel current flows only in one way. For the single-gate vertical channel (SGVC) 3D NAND architecture [1], it is also possible to develop a bottom source structure. The detailed array decoding method is illustrated. In this work, the challenges of bottom source processing and thin poly channel formation are extensively studied. It is found that the two-step poly formation and the bottom recess control are two key factors governing the device initial performance. In general, the two-step poly formation with additional poly spacer etching technique seems to cause degradation of both the poly mobility and device subthreshold slope. Sufficient thermal annealing is needed to recover the damage. Moreover, the bottom connection needs an elegant recess control for better read current as well as bottom ground-select transistor (GSL) device optimizations.
垂直通道(VC) 3D NAND闪存可分为两种通道形成类型:(1)“u型”串，其中BL和源都连接在顶部，因此通道电流以u型方向流动;(2)“底部源”，其中源连接在底部，因此通道电流只以一种方式流动。对于单栅垂直通道(SGVC) 3D NAND架构[1]，也可以开发底源结构。给出了具体的阵列解码方法。在这项工作中，广泛研究了底源处理和薄多通道形成的挑战。研究发现，两步聚晶的形成和底部凹槽的控制是影响器件初始性能的两个关键因素。一般来说，采用额外的聚间隔蚀刻技术的两步聚形成似乎会导致聚迁移率和器件阈下斜率的降低。需要充分的热退火来恢复损伤。此外，底部连接需要一个优雅的凹槽控制，以更好地读取电流以及底部接地选择晶体管(GSL)器件优化。
{"title":"A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering","authors":"S. Lai, H. Lue, T. Hsu, C. Wu, Li-yang Liang, P. Du, C. Chiu, Chih-Yuan Lu","doi":"10.1109/IMW.2016.7493562","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493562","url":null,"abstract":"Vertical channel (VC) 3D NAND Flash may be categorized into two types of channel formation: (1) \"U-turn\" string, where both BL and source are connected at top thus channel current flows in a U-turn way; (2) \"Bottom source\", where source is connected at the bottom thus channel current flows only in one way. For the single-gate vertical channel (SGVC) 3D NAND architecture [1], it is also possible to develop a bottom source structure. The detailed array decoding method is illustrated. In this work, the challenges of bottom source processing and thin poly channel formation are extensively studied. It is found that the two-step poly formation and the bottom recess control are two key factors governing the device initial performance. In general, the two-step poly formation with additional poly spacer etching technique seems to cause degradation of both the poly mobility and device subthreshold slope. Sufficient thermal annealing is needed to recover the damage. Moreover, the bottom connection needs an elegant recess control for better read current as well as bottom ground-select transistor (GSL) device optimizations.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"12 1-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134231596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：