{"title":"ESTD: an emitter switched thyristor with a diverter","authors":"A. Bhalla, T. Chow","doi":"10.1109/DRC.1994.1009402","DOIUrl":null,"url":null,"abstract":"In this paper we present a 600V Emitter Switched Thyristor with a Divener (ESTD, Fig. 2), wlth a novel stnpe design, that incorporates a p-channel diverter adjacent to the floating emitter. The Emitter Switched Thyristor (EST, Fig. 1)[1,2] is a MOS-controlled thyristor that has been demonstrated to have the unique feature of gate controlled current saturation after the thyristor latches on. This current saturation feature is retained in the ESTD. which improves the maximum controllable current of the EST with a small penalty in the forward drop. During turn-off, a negative gate voltage is applied to activate the diverter, creating a p-channel that draws away part of the hole current from the p-well. The hole current flowing under the n+ source is thereby reduced, and latching of the parasitic thyristor is suppressed to higher total current levels, increasing the maximum controllable current. Since the hole current has two alternate paths, i.e. into the cathode contact and out via the diverter MOSFET (Fig. 4), the plasma is squeezed rather like in a GTO. For a linear stripe design, there is a factor of 4 maximum theoretical improvement in controllable current density for the situation of negligible p-channel resistance. The turn-on region and the diverter MOSFET occupy the same region in the device. This leads to an increased JFET resistance in series with the lateral MOSFETs, making it harder to turn the device on. Although the thyristor latching current is relatively unchanged if the floating emitter length is the same as the EST, there is a larger knee in the forward characteristic. (This problem can be alleviated by using a heavier JFET implant.) However, once the thyristor is latched, the difference in the forward drops is small. T h e simulated forward characteristics (Fig. 3) of an EST and ESTD for ~,,,=3p, .tP=0.3ps, show the knee in the ESTD characteristic, and the small increase in forward drop with respect to the EST. (These lifetime values were estimated from the measured IGBT turn-off current waveform on the same wafer, which gave a high level lifetime rn0+ T of 3.3 p.) Snubberless resistive turn-off simulations (1OOV) showed that the EST successfully turned off 200A/cm2, Pp faling at 300A/cm2 while the ESTD failed just above 700A/cm2. In these simulations, a uniform ndrift layer doping of l O \" b K 3 , thickness 50p-1, p-well surface concentration of 1017cm-3, junction depth 3 p , p-base surface concentration 3 X 1017cm-3, junction depth of 3.6pm, n+ surface concentration of 1020cm-3, junction depth l p , and a oxide thickness of lOOnm was assumed. Both ESTs and ESDTs were fabricated on wafers with a 0.02Q-cm, Sopm nepi, 3R-cm n buffer on a p+ substrate. In this study, single-cell devices (300pm long stripes) were compared. These devices were fabricated with six closely spaced floating field rings leading to the main termination designed for a 600V breakdown voltage. This eliminated the need for large p+ areas under the pads connecting the source regions to the termination. The operation of a single-cell could therefore be examined without a parasitic IGBT in parallel with the main device. The measured forward characteristics (Fig. 5 ) of stripe ESTDs with a 7 p diverter gate, 4 p off-gate were compared with those of stripe ESTs with a 1 3 p on-gate, 4 p off-gate, as a function of floating emitter length ( l o p to 3 0 p ) at current densities of 400A/cm2 and 500A/cm2. The forward drop of the 2 0 p floating emitter EST is 2.33V (2.18V simulated) and that of the ESTD is 2.56V (2.23V simulated) at 400A/cm2. The triggering current density at which the main thyristor latches on is compared in the EST and ESTD (Fig. 6), and the decrease in triggering current with increasing with the increase in floating emitter length is expected from the increase in the p-well pinch resistance under the floating emitter. The maximum controllable current density for the same devices as a function of floating emitter length was compared for resistive turn-off at lOOV with V, = k 20V (Fig. 7), showing that the ESTD consistently turns off higher current densities than the EST.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"52nd Annual Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.1994.1009402","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper we present a 600V Emitter Switched Thyristor with a Divener (ESTD, Fig. 2), wlth a novel stnpe design, that incorporates a p-channel diverter adjacent to the floating emitter. The Emitter Switched Thyristor (EST, Fig. 1)[1,2] is a MOS-controlled thyristor that has been demonstrated to have the unique feature of gate controlled current saturation after the thyristor latches on. This current saturation feature is retained in the ESTD. which improves the maximum controllable current of the EST with a small penalty in the forward drop. During turn-off, a negative gate voltage is applied to activate the diverter, creating a p-channel that draws away part of the hole current from the p-well. The hole current flowing under the n+ source is thereby reduced, and latching of the parasitic thyristor is suppressed to higher total current levels, increasing the maximum controllable current. Since the hole current has two alternate paths, i.e. into the cathode contact and out via the diverter MOSFET (Fig. 4), the plasma is squeezed rather like in a GTO. For a linear stripe design, there is a factor of 4 maximum theoretical improvement in controllable current density for the situation of negligible p-channel resistance. The turn-on region and the diverter MOSFET occupy the same region in the device. This leads to an increased JFET resistance in series with the lateral MOSFETs, making it harder to turn the device on. Although the thyristor latching current is relatively unchanged if the floating emitter length is the same as the EST, there is a larger knee in the forward characteristic. (This problem can be alleviated by using a heavier JFET implant.) However, once the thyristor is latched, the difference in the forward drops is small. T h e simulated forward characteristics (Fig. 3) of an EST and ESTD for ~,,,=3p, .tP=0.3ps, show the knee in the ESTD characteristic, and the small increase in forward drop with respect to the EST. (These lifetime values were estimated from the measured IGBT turn-off current waveform on the same wafer, which gave a high level lifetime rn0+ T of 3.3 p.) Snubberless resistive turn-off simulations (1OOV) showed that the EST successfully turned off 200A/cm2, Pp faling at 300A/cm2 while the ESTD failed just above 700A/cm2. In these simulations, a uniform ndrift layer doping of l O " b K 3 , thickness 50p-1, p-well surface concentration of 1017cm-3, junction depth 3 p , p-base surface concentration 3 X 1017cm-3, junction depth of 3.6pm, n+ surface concentration of 1020cm-3, junction depth l p , and a oxide thickness of lOOnm was assumed. Both ESTs and ESDTs were fabricated on wafers with a 0.02Q-cm, Sopm nepi, 3R-cm n buffer on a p+ substrate. In this study, single-cell devices (300pm long stripes) were compared. These devices were fabricated with six closely spaced floating field rings leading to the main termination designed for a 600V breakdown voltage. This eliminated the need for large p+ areas under the pads connecting the source regions to the termination. The operation of a single-cell could therefore be examined without a parasitic IGBT in parallel with the main device. The measured forward characteristics (Fig. 5 ) of stripe ESTDs with a 7 p diverter gate, 4 p off-gate were compared with those of stripe ESTs with a 1 3 p on-gate, 4 p off-gate, as a function of floating emitter length ( l o p to 3 0 p ) at current densities of 400A/cm2 and 500A/cm2. The forward drop of the 2 0 p floating emitter EST is 2.33V (2.18V simulated) and that of the ESTD is 2.56V (2.23V simulated) at 400A/cm2. The triggering current density at which the main thyristor latches on is compared in the EST and ESTD (Fig. 6), and the decrease in triggering current with increasing with the increase in floating emitter length is expected from the increase in the p-well pinch resistance under the floating emitter. The maximum controllable current density for the same devices as a function of floating emitter length was compared for resistive turn-off at lOOV with V, = k 20V (Fig. 7), showing that the ESTD consistently turns off higher current densities than the EST.