Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009442
H.C. Lee, B. Zeghbroeck
High-speed and high-responsivity silicon photodetectors, which can be readily integrated with electronics, would make silicon-based optoelectronic receivers the preferred technology for short distance fiber-optic and free-space optical communication.. However, the long absorption length in silicon (-10 pm at 830 nm) results in detectors with a poor high-speed response. Previous work [l-31 focused on reducing the absorption length by reducing the wavelength (1 pm at 630 nm and 0.1 pm at 400 nm) even though fiber attenuation is more favorable at longer wavelength, whilc light sources are more readily available at 830 nm. In this paper, we present a novel silicon Metal-Semiconductor-Metal (MSM) photodetector structure with a 3.0 GHz bandwidth and 0.17 A/W DC responsivity at 830 nm. The fabrication process is simple and relies on conventional silicon fabrication processes. The structure is an interdigitated MSM detector fabricated on a silicon membrane. The back surface of the membrane is textured to trap the light within the membrane. This detector provides good absorption at longer wavelengths without sacrificing bandwidth. The membrane is created by reactive ion etching using CF4. The back surface is RIE-textured in an Ar/CF4 mixture. Transmission through a 5 pm membrane was measured to be 7.8%, compared to 30% for an untextured membrane, demonstrating the increased absorption. The MSM detector has a finger width of 2.5 km and a finger spacing of 3.75 pm. The bulk detector prior to membrane creation had a responsivity of 0.24 A/W and an internal quantum efficiency of 80% at 5 V. After membrane fabrication, front illumination of the detectors show a responsivity of 0.17 A/W and an internal quantum efficiency of 60%, compared to 0.21 A/W and 45% for back illumination. The transient response of the detectors was obtained by applying 830 nm optical pulses from a current spiked GaAs laser diode. The transient response of the novel detector at 10 V shows a full-width-half-maximum (FWHM) of 74 ps and a fall time of 128 ps. The -3 dB bandwidth is 3.0 GHz (2.7 GHz at 5 V bias) as determined from the fourier transform of the pulse response. For comparison we measured the detector prior to membrane formation. The pulse response showed a FWHM of 267 ps and a bandwidth of 326 MHz at 10 V bias, which clearly demonstrates the effect of the membrane. In summary we have fabricated a novel high-speed silicon detector which can bc integrated with silicon circuits. The detector can be illuminated from either side of the membrane, It was demonstrated to have a superior bandwidth and similar responsivity at 830 nm compared to previously published silicon MSM detectors [l] measured at 630 nm, despite the much larger absorption length.
高速和高响应的硅光电探测器，可以很容易地与电子集成，将使硅基光电接收器成为短距离光纤和自由空间光通信的首选技术。然而，硅中的长吸收长度(在830 nm处-10 pm)导致探测器具有较差的高速响应。先前的工作[l-31]侧重于通过减少波长(630 nm处1 pm和400 nm处0.1 pm)来减少吸收长度，尽管光纤衰减在更长的波长处更有利，而光源在830 nm处更容易获得。在本文中，我们提出了一种新的硅金属-半导体-金属(MSM)光电探测器结构，其带宽为3.0 GHz，在830 nm处具有0.17 a /W的直流响应率。制造过程简单，依赖于传统的硅制造工艺。该结构是在硅膜上制作的交错式MSM探测器。膜的背面有纹理，可以将光困在膜内。这种探测器在不牺牲带宽的情况下，在较长的波长上有很好的吸收。膜是用CF4反应离子蚀刻而成的。后表面在Ar/CF4混合物中呈rie纹理。通过5 pm膜的透射率为7.8%，而无纹理膜的透射率为30%，表明吸收增加。MSM探测器的指宽为2.5公里，指间距为3.75 pm。制备膜前的体探测器在5 V时的响应率为0.24 a /W，内部量子效率为80%。制备膜后，探测器正面照明的响应率为0.17 a /W，内部量子效率为60%，而背面照明的响应率为0.21 a /W，内部量子效率为45%。通过施加830 nm的光脉冲，获得了探测器的瞬态响应。新型探测器在10 V时的瞬态响应显示出74 ps的全宽半最大值(FWHM)和128 ps的下降时间，从脉冲响应的傅里叶变换可以确定-3 dB带宽为3.0 GHz (5 V偏置时为2.7 GHz)。为了比较，我们在膜形成之前测量了检测器。在10v偏置下，脉冲响应的FWHM为267 ps，带宽为326 MHz，这清楚地证明了膜的影响。总之，我们制作了一种新型的高速硅探测器，它可以与硅电路集成。该探测器可以从膜的任何一侧照射，与之前发表的630 nm硅MSM探测器[1]相比，它在830 nm处具有优越的带宽和相似的响应率，尽管吸收长度要大得多。
{"title":"Metal-semiconductor-metal photodiodes on textured silicon membranes","authors":"H.C. Lee, B. Zeghbroeck","doi":"10.1109/DRC.1994.1009442","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009442","url":null,"abstract":"High-speed and high-responsivity silicon photodetectors, which can be readily integrated with electronics, would make silicon-based optoelectronic receivers the preferred technology for short distance fiber-optic and free-space optical communication.. However, the long absorption length in silicon (-10 pm at 830 nm) results in detectors with a poor high-speed response. Previous work [l-31 focused on reducing the absorption length by reducing the wavelength (1 pm at 630 nm and 0.1 pm at 400 nm) even though fiber attenuation is more favorable at longer wavelength, whilc light sources are more readily available at 830 nm. In this paper, we present a novel silicon Metal-Semiconductor-Metal (MSM) photodetector structure with a 3.0 GHz bandwidth and 0.17 A/W DC responsivity at 830 nm. The fabrication process is simple and relies on conventional silicon fabrication processes. The structure is an interdigitated MSM detector fabricated on a silicon membrane. The back surface of the membrane is textured to trap the light within the membrane. This detector provides good absorption at longer wavelengths without sacrificing bandwidth. The membrane is created by reactive ion etching using CF4. The back surface is RIE-textured in an Ar/CF4 mixture. Transmission through a 5 pm membrane was measured to be 7.8%, compared to 30% for an untextured membrane, demonstrating the increased absorption. The MSM detector has a finger width of 2.5 km and a finger spacing of 3.75 pm. The bulk detector prior to membrane creation had a responsivity of 0.24 A/W and an internal quantum efficiency of 80% at 5 V. After membrane fabrication, front illumination of the detectors show a responsivity of 0.17 A/W and an internal quantum efficiency of 60%, compared to 0.21 A/W and 45% for back illumination. The transient response of the detectors was obtained by applying 830 nm optical pulses from a current spiked GaAs laser diode. The transient response of the novel detector at 10 V shows a full-width-half-maximum (FWHM) of 74 ps and a fall time of 128 ps. The -3 dB bandwidth is 3.0 GHz (2.7 GHz at 5 V bias) as determined from the fourier transform of the pulse response. For comparison we measured the detector prior to membrane formation. The pulse response showed a FWHM of 267 ps and a bandwidth of 326 MHz at 10 V bias, which clearly demonstrates the effect of the membrane. In summary we have fabricated a novel high-speed silicon detector which can bc integrated with silicon circuits. The detector can be illuminated from either side of the membrane, It was demonstrated to have a superior bandwidth and similar responsivity at 830 nm compared to previously published silicon MSM detectors [l] measured at 630 nm, despite the much larger absorption length.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123065932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009429
M. Frei, C. Abernathy, T. Chiu, T.R. Fullowan, J. Lothian, R. Montgomery, S. Pearton, F. Ren, P.R. Smith, C. W. Snyder, B. Tseng, J. Weiner, P. Wisk
The devices are fabricated using similar structures grown by MOMBE', with Sn and C as dopants. The growth sequence includes a 62 nm GaAs base ( p = 7 ~ 1 0 ' ~ c m ~ ) , a 7 nm GaAs undoped spacer, and a 80 nm Alo.25 Gao.75 As emitter (n= 6x lo'* cm). The main fabrication technology uses a self-aligned process based on dry etching with AuGe metallization and ion-implant isolation, This process, which we refer to as the "implant process", is similar to that described in ref. 2, but with a tri-layer lift-off ste for the base metallization and higher implant doses. The implant includes total doses of 1 . 8 ~ 1OI6 cmH+ and 1014cm-2 F+ and is followed by annealing at 53OOC. A second process (the "W process") replaces the AuGe metallization with WSi, and the ion-implantation with mesa isolation and a semiplanarized geometry.
{"title":"Characterization of degradation mechanisins in GaAs/AlGaas heterojunction bipolar transistors","authors":"M. Frei, C. Abernathy, T. Chiu, T.R. Fullowan, J. Lothian, R. Montgomery, S. Pearton, F. Ren, P.R. Smith, C. W. Snyder, B. Tseng, J. Weiner, P. Wisk","doi":"10.1109/DRC.1994.1009429","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009429","url":null,"abstract":"The devices are fabricated using similar structures grown by MOMBE', with Sn and C as dopants. The growth sequence includes a 62 nm GaAs base ( p = 7 ~ 1 0 ' ~ c m ~ ) , a 7 nm GaAs undoped spacer, and a 80 nm Alo.25 Gao.75 As emitter (n= 6x lo'* cm). The main fabrication technology uses a self-aligned process based on dry etching with AuGe metallization and ion-implant isolation, This process, which we refer to as the \"implant process\", is similar to that described in ref. 2, but with a tri-layer lift-off ste for the base metallization and higher implant doses. The implant includes total doses of 1 . 8 ~ 1OI6 cmH+ and 1014cm-2 F+ and is followed by annealing at 53OOC. A second process (the \"W process\") replaces the AuGe metallization with WSi, and the ion-implantation with mesa isolation and a semiplanarized geometry.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124995785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009400
R. Siergiej, A. Agarwal, A. Burk, R. C. Clarke, H. Hobgood, P. McMullin, P. A. Orphanos, S. Sriram, T.J. Smith, C. Brandt
Silicon carbide is well suited for high frequency power devices due to its high saturated electron velocity, high thermal conductivity, and high-breakdown field strength. While much of the focus of silicon carbide device research has been to demonstrate high frequency MESFET transistors, we describe a silicon carbide MOSFET with superior drive, gain, and high temperature performance. In addition, these MOSFET's have been configured in demonstration circuits revealing the first silicon carbide monolithic integrated circuits. One inch diameter, 6H p-type silicon carbide wafers were used as the starting material. Appropriately doped nand n+ epitaxial layers were grown by the chemical vapor deposition pmcess. The devices were mesa isolated using reactive ion etching. The gate oxide was grown with a thermal oxidation. Contacts to the drain and source were made with nickel and sintered using RTA. Electron beam direct write lithography was used to define the gates to obtain precise alignment and dimensional control.
{"title":"Novel silicon carbide mosfet's for monolithic integrated circuits","authors":"R. Siergiej, A. Agarwal, A. Burk, R. C. Clarke, H. Hobgood, P. McMullin, P. A. Orphanos, S. Sriram, T.J. Smith, C. Brandt","doi":"10.1109/DRC.1994.1009400","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009400","url":null,"abstract":"Silicon carbide is well suited for high frequency power devices due to its high saturated electron velocity, high thermal conductivity, and high-breakdown field strength. While much of the focus of silicon carbide device research has been to demonstrate high frequency MESFET transistors, we describe a silicon carbide MOSFET with superior drive, gain, and high temperature performance. In addition, these MOSFET's have been configured in demonstration circuits revealing the first silicon carbide monolithic integrated circuits. One inch diameter, 6H p-type silicon carbide wafers were used as the starting material. Appropriately doped nand n+ epitaxial layers were grown by the chemical vapor deposition pmcess. The devices were mesa isolated using reactive ion etching. The gate oxide was grown with a thermal oxidation. Contacts to the drain and source were made with nickel and sintered using RTA. Electron beam direct write lithography was used to define the gates to obtain precise alignment and dimensional control.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116811417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009450
G. Trombley, C. Havasy, R.G.-H. Lee, R. Reston, C. Ito, T. Jenkins
High temperature electronics (HTE) are required for automotive, aircraft, space and other applications exposed to thermal extremes. Many HTE efforts have focused on very wide bandgap semiconductors (>2.5eV) such as Sic, GaN and diamond [l], [2]. However, GaAs (a more mature technology) also shows promise for high temperature applications (<400"C) because it provides a reasonably wide bandgap (1.42eV) with high mobility. Unfortunately, when GaAs MESFETs are evaluated at temperatures greater than 250°C large subthreshold drain currents degrade device performance by reducing switching ratios and increasing output conductances [3]. A potential solution to the problem of large subthreshold currents is explored in this investigation. By incorporating an undoped AMs buffer layer beneath the active channel of a GaAs MESFET, a marked reduction in subthreshold current is observed at temperatures as high as 350°C.
{"title":"High temperature device characterstics of GaAs MESFETs fabricated with an AlAs buffer layer","authors":"G. Trombley, C. Havasy, R.G.-H. Lee, R. Reston, C. Ito, T. Jenkins","doi":"10.1109/DRC.1994.1009450","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009450","url":null,"abstract":"High temperature electronics (HTE) are required for automotive, aircraft, space and other applications exposed to thermal extremes. Many HTE efforts have focused on very wide bandgap semiconductors (>2.5eV) such as Sic, GaN and diamond [l], [2]. However, GaAs (a more mature technology) also shows promise for high temperature applications (<400\"C) because it provides a reasonably wide bandgap (1.42eV) with high mobility. Unfortunately, when GaAs MESFETs are evaluated at temperatures greater than 250°C large subthreshold drain currents degrade device performance by reducing switching ratios and increasing output conductances [3]. A potential solution to the problem of large subthreshold currents is explored in this investigation. By incorporating an undoped AMs buffer layer beneath the active channel of a GaAs MESFET, a marked reduction in subthreshold current is observed at temperatures as high as 350°C.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123509847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009398
W. Bronner, J. Hornung, K. Kohler, W. Benz, E. Olander, J. Ralston
{"title":"Technology for monolithic integration of ridge-guided quantum well lasers and AlGaAs/GaAs/AlGaAs-HEMT electronics","authors":"W. Bronner, J. Hornung, K. Kohler, W. Benz, E. Olander, J. Ralston","doi":"10.1109/DRC.1994.1009398","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009398","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114747331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009419
J. Shen, G. Kramer, S. Tehrani, H. Goronkin, T. Zhu, R. Tsui
We have fabricated SRAM's based on resonant interband tunneling diodes in the InAs/AlSb/GaSb material sys- tem. The bistability and the switching principles are demon- strated. Numerical simulations of the memory characteristics of the SRAM cell are performed and used for comparing with experiments. Several key issues involving the applications of the device are also discussed. (a) (b) Fig. 1. The equivalent circuit and layer structure of the RITD-based SRAM's. The cell is selected when a differential voltage between VD and V,, are. applied. The structure is based on the InAs/AlSb/GaSb material system. (a) A scheme that uses a tunneling diode connected to the middle node. (b) The cross section of an SRAM cell.
{"title":"Static random access memories based on resonant interband tunneling diodes in the InAs/GaSb/AlSb material system","authors":"J. Shen, G. Kramer, S. Tehrani, H. Goronkin, T. Zhu, R. Tsui","doi":"10.1109/DRC.1994.1009419","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009419","url":null,"abstract":"We have fabricated SRAM's based on resonant interband tunneling diodes in the InAs/AlSb/GaSb material sys- tem. The bistability and the switching principles are demon- strated. Numerical simulations of the memory characteristics of the SRAM cell are performed and used for comparing with experiments. Several key issues involving the applications of the device are also discussed. (a) (b) Fig. 1. The equivalent circuit and layer structure of the RITD-based SRAM's. The cell is selected when a differential voltage between VD and V,, are. applied. The structure is based on the InAs/AlSb/GaSb material system. (a) A scheme that uses a tunneling diode connected to the middle node. (b) The cross section of an SRAM cell.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133750457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009444
I. Tan, J. Bowers, E. Hu, B. Miller
{"title":"High quantum efficiency and narrow detection bandwidth of a resonant In/sub 0.53/Ga/sub 0.47/As photodector using the wafer fusing","authors":"I. Tan, J. Bowers, E. Hu, B. Miller","doi":"10.1109/DRC.1994.1009444","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009444","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127287308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009422
T. Wang, C. Huang, T. Chang, J. Chou, C. Chang
considerable interest. In this work, we develop an interface trap assisted two-step tunneling model in n-MOSFET's, which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band. In our model, the electron occupation factor of the interface traps &(E) is equated below since for the number of trapped electrons in the interface traps is unchanged in steady state. Recently, the effect of a ot carrier stress generated interface traps on GIDL has received
{"title":"Lateral field enhanced band-trap-band tunneling current in a 0.5/spl mu/m \"OFF\" state MOSFET","authors":"T. Wang, C. Huang, T. Chang, J. Chou, C. Chang","doi":"10.1109/DRC.1994.1009422","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009422","url":null,"abstract":"considerable interest. In this work, we develop an interface trap assisted two-step tunneling model in n-MOSFET's, which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band. In our model, the electron occupation factor of the interface traps &(E) is equated below since for the number of trapped electrons in the interface traps is unchanged in steady state. Recently, the effect of a ot carrier stress generated interface traps on GIDL has received","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121394723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009435
D. Robbins, M. Stanaway, S. Millidge, W. Y. Leong, R. Carline, N. Gordon
We report the first systematic study of p-Si,-,Ge,/Si quantum well infrared photodetectors (QWIPs) grown by low pressure vapour phase epitaxy, including detailed structural, electrical and opticaI characterisation. The growth method is compatible with industrial production, and the devices are potentially suitable as photoconductive detectors operating in normal incidence in large 2-D thermal imaging arrays. Structures have been grown with different numbers of periods and different QW widths, Si,-,Ge, compositions and doping levels. The Si barrier layers are typically 50nm thick and the p-Si contacts are ohmic. Representative characteristics for a 200pm diameter, mesa-isolated, 50 period device under 2V bias are a peak (7.2pm) quantum efficiency of 1 % for a single optical pass, differential resistances of 16MQ at 56K and 170kQ at 75K, and a 1OkHz noise current of 6.5E-13 A/*z at 77K.
我们报道了第一个通过低压气相外延生长的p-Si，- Ge，/Si量子阱红外探测器(qwip)的系统研究，包括详细的结构，电学和光学表征。该生长方法与工业生产兼容，并且该器件可能适合作为在大型二维热成像阵列中正常入射下工作的光导探测器。不同的周期数和不同的量子阱宽度、Si、-、Ge、成分和掺杂水平生长了不同的结构。硅势垒层通常为50nm厚，p-Si接触是欧姆的。在2V偏置下，直径200pm、台面隔离、50周期器件的代表性特征是单光通的峰值(7.2pm)量子效率为1%，在56K时差分电阻为16MQ，在75K时差分电阻为170kQ，在77K时噪声电流为6.5E-13 a /*z。
{"title":"Characteristics of long wavelength infrared detectors using p-Si/sub 1-x/Ge/sub x//Si multiple quantum wells","authors":"D. Robbins, M. Stanaway, S. Millidge, W. Y. Leong, R. Carline, N. Gordon","doi":"10.1109/DRC.1994.1009435","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009435","url":null,"abstract":"We report the first systematic study of p-Si,-,Ge,/Si quantum well infrared photodetectors (QWIPs) grown by low pressure vapour phase epitaxy, including detailed structural, electrical and opticaI characterisation. The growth method is compatible with industrial production, and the devices are potentially suitable as photoconductive detectors operating in normal incidence in large 2-D thermal imaging arrays. Structures have been grown with different numbers of periods and different QW widths, Si,-,Ge, compositions and doping levels. The Si barrier layers are typically 50nm thick and the p-Si contacts are ohmic. Representative characteristics for a 200pm diameter, mesa-isolated, 50 period device under 2V bias are a peak (7.2pm) quantum efficiency of 1 % for a single optical pass, differential resistances of 16MQ at 56K and 170kQ at 75K, and a 1OkHz noise current of 6.5E-13 A/*z at 77K.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132603287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009426
E. Dubois, P. Bricout
IIntroduction Silicon technology is now entering in the sub 0.1 pm range of channel length. In this deep submicron regime, the operating voltage has to be reduced for power dissipation, device reliability and speed performance considerations [ 11. Several scaling analysis have been proposed to explore the ultimate limits of MOSFETs. According to the technological complexity, the outer limit of scaling was found to be 50 and 30 nm in [2] and [3], for epitaxial and dual gate structures, respectively. The control of short channel effects (e.g. threshold voltage roll-off and subthreshold swing increase) severely limits the scaling below 50nm of channel length in conventional planar structures as in [2]. On the other hand, the dual gate structure proposed in [3] exhibits reasonable subthreshold characteristics but still represents a technological challenge and requires gate work function controllability for threshold adjustment. A recessed channel structure is proposed as a technological compromise between dual gate and conventional planar structures. The immunity with respect to short channel effects and the current drive capabilities are extensively studied using drift-diffusion and Monte Carlo simulations.
{"title":"Short channel immunity and current drive capabilities of recessed mosfets in the sub-50 mn regime","authors":"E. Dubois, P. Bricout","doi":"10.1109/DRC.1994.1009426","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009426","url":null,"abstract":"IIntroduction Silicon technology is now entering in the sub 0.1 pm range of channel length. In this deep submicron regime, the operating voltage has to be reduced for power dissipation, device reliability and speed performance considerations [ 11. Several scaling analysis have been proposed to explore the ultimate limits of MOSFETs. According to the technological complexity, the outer limit of scaling was found to be 50 and 30 nm in [2] and [3], for epitaxial and dual gate structures, respectively. The control of short channel effects (e.g. threshold voltage roll-off and subthreshold swing increase) severely limits the scaling below 50nm of channel length in conventional planar structures as in [2]. On the other hand, the dual gate structure proposed in [3] exhibits reasonable subthreshold characteristics but still represents a technological challenge and requires gate work function controllability for threshold adjustment. A recessed channel structure is proposed as a technological compromise between dual gate and conventional planar structures. The immunity with respect to short channel effects and the current drive capabilities are extensively studied using drift-diffusion and Monte Carlo simulations.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134430624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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