The Fault Tolerant CMOS Logical Element of Matching for a Content-Addressable Memory

Abstract

The CMOS logical element of matching contains the STG DICE memory cell with transistors divided into two groups together with transistors of the output combinational logic. A single nuclear particle generates charges along its track. The collection of an induced charge just one group of transistors does not lead to the failure of the logical state of the cell. The results of the simulation presents for the element of matching as a part of an associative memory. It shows the hardness to a fault of the cell up to 70 MeV×cm2/mg of the linear energy transfer on the tracks of single particles. Noise pulses generate mostly in the output logic at the mode when the output has to be equal “1”. The correct results of matching data in registers of cells, when a noise pulse is, get more reliable using the summing circuits on the combinational logic but not using match lines.