A 12-bit 200KS/s SAR ADC with digital self-calibration

Xiaojie Zhang, Maodong Wang, Liyang Guo, Xinghua Wang
{"title":"A 12-bit 200KS/s SAR ADC with digital self-calibration","authors":"Xiaojie Zhang, Maodong Wang, Liyang Guo, Xinghua Wang","doi":"10.1109/IAEAC.2017.8054480","DOIUrl":null,"url":null,"abstract":"Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving 1-bit improvement of ENOB. Simulation results show that, when the input signal is 46K, the ADC fulfills an SNDR of 71.55dB and an SFDR of 91.82dB with a 200KS/s sampling rate, while the ADC only can achieve an SNDR of 65.85dB and an SFDR of 78.83dB before calibration. With the ENOB of 11.59 bit, the self-calibration SAR ADC consumes 336μW at 1.8 V power supply.","PeriodicalId":432109,"journal":{"name":"2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAEAC.2017.8054480","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving 1-bit improvement of ENOB. Simulation results show that, when the input signal is 46K, the ADC fulfills an SNDR of 71.55dB and an SFDR of 91.82dB with a 200KS/s sampling rate, while the ADC only can achieve an SNDR of 65.85dB and an SFDR of 78.83dB before calibration. With the ENOB of 11.59 bit, the self-calibration SAR ADC consumes 336μW at 1.8 V power supply.
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一个带数字自校准的12位200KS/s SAR ADC
针对神经信号检测系统的应用,设计了一种采用中芯国际0.18 μm工艺制作的12位200KS/s高分辨率逐次逼近模数转换器(SAR ADC)。提出了一种优化的数字自校准技术,利用校正电容阵列对比较器的静态偏置和电容阵列的失配进行校正,实现了ENOB的1位提升。仿真结果表明,当输入信号为46K时,当采样率为200KS/s时,ADC的SNDR为71.55dB, SFDR为91.82dB,而校准前ADC的SNDR为65.85dB, SFDR为78.83dB。自校准SAR ADC的ENOB为11.59位,在1.8 V电源下功耗为336μW。
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