Optimal Schemes for ADC BIST Based on Histogram

Abstract

Two testing time reducing schemes of histogram-based BIST (built-in self test) for testing of ADC IPs (intellectual property) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (differential nonlinearity) and INL (integral nonlinearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated