An ultra-low power deep sub-micron fast start-up circuit with added line regulation

Abstract

In this paper an ultra low power consumption (in the range of pW) start-up circuit is introduced. In the proposed circuit configuration no resistor nor capacitor are included and only normal CMOS devices with low device count (only three devices) are used. In this manner the active area of the circuit is extremely reduced. The circuit shows a very fast reaction time of less than 2µs that makes it attractive for many real time applications. The proposed circuit has the feature of acting as a composite transistor in the normal active mode of the targeted self biased circuit helping to improve its line regulation performance. This is a benefit of the proposed start-up circuit which is completely in line with the purpose of using the self- biased configurations in voltage reference circuits. The circuit is designed and simulated in a commercial 40nm technology using Cadence tools. The parasitic effects of the layout are also included in the simulations.