An ultra-low power deep sub-micron fast start-up circuit with added line regulation

Asghar Bahramali, M. López-Vallejo, C. López-Barrio
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Abstract

In this paper an ultra low power consumption (in the range of pW) start-up circuit is introduced. In the proposed circuit configuration no resistor nor capacitor are included and only normal CMOS devices with low device count (only three devices) are used. In this manner the active area of the circuit is extremely reduced. The circuit shows a very fast reaction time of less than 2µs that makes it attractive for many real time applications. The proposed circuit has the feature of acting as a composite transistor in the normal active mode of the targeted self biased circuit helping to improve its line regulation performance. This is a benefit of the proposed start-up circuit which is completely in line with the purpose of using the self- biased configurations in voltage reference circuits. The circuit is designed and simulated in a commercial 40nm technology using Cadence tools. The parasitic effects of the layout are also included in the simulations.
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一个超低功耗深亚微米快速启动电路,增加了线路调节
本文介绍了一种超低功耗(pW范围内)启动电路。在提议的电路配置中,不包括电阻和电容,仅使用具有低器件计数(仅三个器件)的普通CMOS器件。这样,电路的有源面积就大大减小了。该电路显示出小于2µs的快速反应时间,这使得它对许多实时应用具有吸引力。该电路具有在目标自偏置电路的正常有源模式下充当复合晶体管的特点,有助于提高其线路调节性能。这是所提出的启动电路的一个优点,它完全符合在参考电压电路中使用自偏置配置的目的。该电路采用商用40nm技术,使用Cadence工具进行设计和仿真。在仿真中还考虑了布局的寄生效应。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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