CA-CSTP: a new BIST architecture for sequential circuits

F. Corno, M. Sonza Reorda, Giovanni Squillero, M. Violante
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引用次数: 8

Abstract

Circular Self-Test Path (CSTP) is an attractive technique for implementing BIST in sequential circuits; unfortunately, there are cases in which the fault coverage it attains is unacceptably low. This paper proposes a new architecture, named CA-CSTP, which overcomes these limitations and always reaches a high fault coverage by exploiting a slightly more complex chain cell based on a Cellular Automata architecture. Experimental results show the effectiveness of our proposal.
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CA-CSTP:时序电路的一种新的BIST体系结构
圆形自测路径(CSTP)是在顺序电路中实现BIST的一种有吸引力的技术;不幸的是,在某些情况下,它所获得的故障覆盖率低得令人无法接受。本文提出了一种新的体系结构CA-CSTP,该体系结构克服了这些限制,利用基于元胞自动机体系结构的稍微复杂的链单元,总能达到较高的故障覆盖率。实验结果表明了该方法的有效性。
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