J. Jatin, M. Monishmurali, S. K. Gautam, M. Shrivastava
{"title":"Performance and Reliability Co-Design of HV devices in Vertically Stacked Nanosheet Technology","authors":"J. Jatin, M. Monishmurali, S. K. Gautam, M. Shrivastava","doi":"10.1109/ICEE56203.2022.10118336","DOIUrl":null,"url":null,"abstract":"In this work, for the first time, Drain-Extended vertically stacked Nanosheet-based HV device has been studied in the context of System-On-Chip (SoC) integration. Physical insights into the device performance and ESD reliability are elaborated using 3D TCAD process simulations. Finally, the performance and reliability co-design guidelines related to HV devices in Nanosheets technology have been discussed comprehensively.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEE56203.2022.10118336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, for the first time, Drain-Extended vertically stacked Nanosheet-based HV device has been studied in the context of System-On-Chip (SoC) integration. Physical insights into the device performance and ESD reliability are elaborated using 3D TCAD process simulations. Finally, the performance and reliability co-design guidelines related to HV devices in Nanosheets technology have been discussed comprehensively.
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