{"title":"A 0.5/spl mu/m CMOS low-distortion low-power line driver with embedded digital adaptive bias algorithm for integrated ADSL analog front-ends","authors":"M. Ingels, S. Bojja, P. Wouters","doi":"10.1109/ISSCC.2002.992243","DOIUrl":null,"url":null,"abstract":"A 5V 0.5/spl mu/m CMOS line driver has distortion <-65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5/spl Omega/ load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992243","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 5V 0.5/spl mu/m CMOS line driver has distortion <-65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5/spl Omega/ load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end.
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