Path-delay fault simulation for circuits with large numbers of paths for very large test sets

Abstract

We propose an exact non-enumerative path-delay fault simulation technique for combinational circuits using very large test sets. We focus on combinational circuits that contain very large numbers of path delay faults, for example, c6288 that has about 2/spl times/10/sup 20/ possible path-delay faults. Enumerative fault simulators simply cannot handle such circuits. Existing non-enumerative fault simulators work for small test sets only. The proposed method uses the mathematical principle of inclusion and exclusion and handles the large number of tests using a novel encoding technique.