K. Yoshikawa, E. Sakagami, S. Mori, N. Arai, K. Narita, Y. Yamaguchi, Y. Ohshima, K. Naruke
{"title":"A 3.3 V operation nonvolatile memory cell technology","authors":"K. Yoshikawa, E. Sakagami, S. Mori, N. Arai, K. Narita, Y. Yamaguchi, Y. Ohshima, K. Naruke","doi":"10.1109/VLSIT.1992.200636","DOIUrl":null,"url":null,"abstract":"The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200636","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<>
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