{"title":"An 18 mW 1800 MHz quadrature demodulator in 0.18 /spl mu/m CMOS","authors":"D. Pfaff, Q. Huang","doi":"10.1109/ISSCC.2002.993026","DOIUrl":null,"url":null,"abstract":"A demodulator has been designed which consists of a 3.6 GHz VCO, a 3.8 mA current-mode divider for the I/Q generation, and two single-ended input double-balanced mixers. The IC consumes 10 mA at 1.8 V, and has -114 dBc phase noise at 100 kHz offset, 40 dB image rejection, 14 dB DSB noise figure and 8.5 dBm IIP3.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.993026","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A demodulator has been designed which consists of a 3.6 GHz VCO, a 3.8 mA current-mode divider for the I/Q generation, and two single-ended input double-balanced mixers. The IC consumes 10 mA at 1.8 V, and has -114 dBc phase noise at 100 kHz offset, 40 dB image rejection, 14 dB DSB noise figure and 8.5 dBm IIP3.
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