{"title":"Flip-chip assembly development via modified reflowable underfill process","authors":"P. Miao, Y. Chew, Tie Wang, L. Foo","doi":"10.1109/ECTC.2001.927714","DOIUrl":null,"url":null,"abstract":"This paper presents two flip-chip assembly processes that enable an underfill with higher filler loading to be incorporated into the package. The first process includes dispensing the underfill containing higher filler loading on substrate surface, followed by chip placement and solder reflow under thermal compression. Apart from this, the second approach is virtually the modification of standard reflowable underfill process. The underfill with higher filler loading was spin-coated onto a bumped wafer surface and then cured. Subsequently, the top portion of bumps was exposed by laser treatment prior to wafer dicing. The diced chips with low CTE coating on the surface already were assembled via standard reflowable underfill process that includes dispensing reflowable underfill, chip placement and solder reflow through reflow oven.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2001.927714","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper presents two flip-chip assembly processes that enable an underfill with higher filler loading to be incorporated into the package. The first process includes dispensing the underfill containing higher filler loading on substrate surface, followed by chip placement and solder reflow under thermal compression. Apart from this, the second approach is virtually the modification of standard reflowable underfill process. The underfill with higher filler loading was spin-coated onto a bumped wafer surface and then cured. Subsequently, the top portion of bumps was exposed by laser treatment prior to wafer dicing. The diced chips with low CTE coating on the surface already were assembled via standard reflowable underfill process that includes dispensing reflowable underfill, chip placement and solder reflow through reflow oven.