Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation

V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. Jeong, Y. Ko, C. H. Lee, J. Sim, M. Angyal, E. Crabbé
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Abstract

This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.
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7nm FinFET产品中离散FET监视器的设计与分析,用于稳健技术验证
本文提出了两种现象,通过类似产品的模拟布局设计的实验(do)捕获,否则难以捕捉铸造基线测试结构。这种产品驱动的测试结构对于早期发现良率减损因素和在无晶圆厂设计环境中可靠地验证技术至关重要。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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