An efficient method of applying hot-carrier reliability simulation to logic design

Abstract

This paper presents an efficient application of hot carrier reliability simulation to 0.18 /spl mu/m and 0.14 /spl mu/m gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products which were screened to check whether the rise time restrictions were met. At 200 MHz, maximum rise time (0-100%) triseMAX was 0.8 ns (17% of duty) under /spl Delta/td/td=5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.