A. Carter, J. Law, E. Lobisser, G. Burek, W. Mitchell, B. Thibeault, A. Gossard, M. Rodwell
{"title":"60 nm gate length Al2O3 / In0.53Ga0.47As gate-first MOSFETs using InAs raised source-drain regrowth","authors":"A. Carter, J. Law, E. Lobisser, G. Burek, W. Mitchell, B. Thibeault, A. Gossard, M. Rodwell","doi":"10.1109/DRC.2011.5994402","DOIUrl":null,"url":null,"abstract":"Given adequately low source/drain (S/D) access resistivity and dielectric interface trap density (R<inf>access</inf> < 50 Ω-µ,<sup>1</sup> and D<inf>it</inf> < 2 · 10<sup>12</sup> cm<sup>−2</sup> eV<sup>−1,2</sup> respectively), InGaAs MOSFETs will provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT). The access resistance must be obtained in a self-aligned structure with a contacted gate pitch ∼4 times the physical gate length (L<inf>g</inf>), e.g. 116 nm at 32 nm L<inf>g</inf>,<sup>3</sup> while control of short channel effects demands that the S/D region depth be only a fraction of gate length; low-resistance, ultra-shallow fully self-aligned III-V MOS processes must therefore be developed. Here we report a 60 nm L<inf>g</inf> In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET fabricated in a gate-first process with self-aligned raised InAs S/D access regions formed by MBE regrowth. The devices have a peak drive current of 1.36 mA/µm at V<inf>ds</inf> = 1.25 V and V<inf>gs</inf> = 3 V and an R<inf>on</inf> = 341 ohm-µm. To our knowledge this is the lowest R<inf>on</inf> and smallest L<inf>g</inf> reported to date for In<inf>0.53</inf>Ga<inf>0.47</inf>As surface channel MOSFETs.<sup>4</sup>","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"69th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2011.5994402","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Given adequately low source/drain (S/D) access resistivity and dielectric interface trap density (Raccess < 50 Ω-µ,1 and Dit < 2 · 1012 cm−2 eV−1,2 respectively), InGaAs MOSFETs will provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT). The access resistance must be obtained in a self-aligned structure with a contacted gate pitch ∼4 times the physical gate length (Lg), e.g. 116 nm at 32 nm Lg,3 while control of short channel effects demands that the S/D region depth be only a fraction of gate length; low-resistance, ultra-shallow fully self-aligned III-V MOS processes must therefore be developed. Here we report a 60 nm Lg In0.53Ga0.47As MOSFET fabricated in a gate-first process with self-aligned raised InAs S/D access regions formed by MBE regrowth. The devices have a peak drive current of 1.36 mA/µm at Vds = 1.25 V and Vgs = 3 V and an Ron = 341 ohm-µm. To our knowledge this is the lowest Ron and smallest Lg reported to date for In0.53Ga0.47As surface channel MOSFETs.4