S. Yinger, F. Lee, R. Huang, K. Schneider, E. Wang, K. F. Smith, M. Penugonda, S. Jacobs, T. Carter
{"title":"HBT gate array for 5 GHz ASICs","authors":"S. Yinger, F. Lee, R. Huang, K. Schneider, E. Wang, K. F. Smith, M. Penugonda, S. Jacobs, T. Carter","doi":"10.1109/GAAS.1993.394493","DOIUrl":null,"url":null,"abstract":"A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. Chip size is 2.2 mm /spl times/ 2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 watts. The top level gate delay is 55 ps for a fanout of one and 60 fF load.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"141 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th Annual GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1993.394493","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. Chip size is 2.2 mm /spl times/ 2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 watts. The top level gate delay is 55 ps for a fanout of one and 60 fF load.<>
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