Simulation of non-classical faults on the gate level-fault modeling

Abstract

A two-step approach is used to increase the accuracy of fault modeling without sacrificing the efficiency of fault simulation and test pattern generation on the gate level. First, low level faults are mapped onto the gate level and a data base with gate level faults is created. In a second step, fault simulation is performed using this data base. A gate level fault simulator has been modified to perform the simulations. This paper describes the first step and presents a method which maps low level faults onto gate level faults. Existing gate level fault models are extended and new gate level fault models are introduced. In order to demonstrate the feasibility of the approach electrical level shorts and opens have been mapped onto gate level faults for two typical CMOS libraries. For these libraries all shorts and opens can be described accurately by gate level faults.<>