Investigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memory

Abstract

Factors affecting SET-disturb failure time (τf) in a tungsten oxide resistive switching memory including SET/RESET cycling stress, resistance window in operation and SET-disturb voltage are investigated. A SET-disturb failure time in high resistance state (HRS) may degrade by orders of magnitude in a post-cycling cell. The degradation is attributed to the formation of a current percolation path of cycling stress-generated traps. A one-dimensional percolation model is proposed for the τf degradation. The dependence of τf on resistance window in operation is characterized. We find that τf is greatly affected by the current level of LRS. The strong LRS dependence of τf is attributed to a small Weibull slope of τf. In addition, we perform statistical characterizations of τf at different SET-disturb voltages. A relationship between τf and a SET-disturb voltage in a stressed cell is given.