FPGA and ASIC Implementation and Comparison of Multipliers

Abstract

The multipliers find extensive use in today’s digital world and are even fundamental components in many signal processing applications. This paper presents the implementation and comparison of three types of 4-bit and 8-bit multipliers i.e. Array, Wallace and Baugh Wooley. The implementation is done on both the FPGA and ASIC to compare the designs. The FPGA implementation is done on NEXYS 4 DDR which is equipped with Xilinx Artix-7 FPGA. The ASIC implementation is done using Cadence and Standard Cell Library 90 nm gpdk (generic process design kit). The results indicate that the Baugh Wooley incurs the minimum delay in the FPGA implementation while as the Wallace tree incurs minimum Power Delay Product in the ASIC implementation. The Baugh Wooley is the least area consuming architecture for both the FPGA and the ASIC implementation.