Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263016
K. Johguchi
Recently, there are many kinds of non-volatile memories like NAND flash, MRAM, PCM and ReRAM. Since there is no perfect non-volatile memories, a co-design of device, circuits and systems is essential in order to achieve high performance and reliability with low cost and power consumption. To reach this goal, this paper proposes a hybrid solid-state drive based storage system with optimum circuits to manage each non-volatile memory characteristics.
{"title":"A Smart Hybrid Solid-State-Drive Storage System based on Nonvolatile Storage-Class-Memories : Device, Circuit Design and Architecture","authors":"K. Johguchi","doi":"10.1109/ISDCS49393.2020.9263016","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263016","url":null,"abstract":"Recently, there are many kinds of non-volatile memories like NAND flash, MRAM, PCM and ReRAM. Since there is no perfect non-volatile memories, a co-design of device, circuits and systems is essential in order to achieve high performance and reliability with low cost and power consumption. To reach this goal, this paper proposes a hybrid solid-state drive based storage system with optimum circuits to manage each non-volatile memory characteristics.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121036696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263008
N. C. Mandal, Pritam Banerjee, A. Nandi, Sukanta Bose, G. Das, Shantanu Maity, P. Chaudhuri, H. Saha
Selection of suitable metal-oxide type dielectric passivation layer enhances the open circuit voltage of the Passivated Emitter Rear Contact (PERC) solar cell to a great extent. Incorporation of Aluminium oxide (Al2O3) as passivation layer has been a common practice for the fabrication of PERC solar cell both in industry and research laboratory. However, the optically unmatched refractive index of Al2O3 does not redirect the transmitted photons (Wavelength ranging 900nm to 1100nm) through ~180µm thick c-Si p-type substrate to the solar cell. Hafnium oxide (HfO2) with optically matched RI exhibits comparable passivation property. If HfO2 can be used instead of Al2O3 increase the possibility of redirecting the transmitted photons to the solar cell again without compromising the passivation property, which may increases the solar cell performance. It has been observed that 93% transmitted photons can be reflected back to the solar cell structure for optimized double dielectric stack.
{"title":"Optimization of stacked di-electric bilayer at rear side of PERC solar cell for better light management","authors":"N. C. Mandal, Pritam Banerjee, A. Nandi, Sukanta Bose, G. Das, Shantanu Maity, P. Chaudhuri, H. Saha","doi":"10.1109/ISDCS49393.2020.9263008","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263008","url":null,"abstract":"Selection of suitable metal-oxide type dielectric passivation layer enhances the open circuit voltage of the Passivated Emitter Rear Contact (PERC) solar cell to a great extent. Incorporation of Aluminium oxide (Al2O3) as passivation layer has been a common practice for the fabrication of PERC solar cell both in industry and research laboratory. However, the optically unmatched refractive index of Al2O3 does not redirect the transmitted photons (Wavelength ranging 900nm to 1100nm) through ~180µm thick c-Si p-type substrate to the solar cell. Hafnium oxide (HfO2) with optically matched RI exhibits comparable passivation property. If HfO2 can be used instead of Al2O3 increase the possibility of redirecting the transmitted photons to the solar cell again without compromising the passivation property, which may increases the solar cell performance. It has been observed that 93% transmitted photons can be reflected back to the solar cell structure for optimized double dielectric stack.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123710482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263013
S. Bhattacharya, A. Luo, S. Dutta, M. Miura-Mattausch, H. Mattausch
We propose a surface-recognition-based speed- adjustment system for humanoid robot during walking on different surfaces. Two different types of surfaces are considered in the reported experiment (example, rough and smooth surface). Force-sensors, classification unit and external- controller-circuits are applied for surface-recognition and speed-adjustment. For surface-recognition the Euclidean distance is used to calculate the nearest-neighbor reference pattern for the feature of the waking pattern generated online. The mean-absolute-value (MAV) feature vector is used to classify two different surfaces. To distinguish two different surfaces, the hardware accelerated decision-signals are generated across LEDs in the form of analog voltages (maximum peak voltage 212 mV for rough-surface and 147 mV for smooth surfaces respectively with detection time 2.8 s and 1.5 s). The external-controller-circuit is used for speed- adjustment using decision-signal coming from LED. It is observed that, when robot is moving from rough-surfaces to smooth-surfaces, the speed of the robot motion changes from 190 frames/stride (i.e. slow-speed) to 160 frames/stride (i.e. medium-speed) with 4.9 s transition time, whereas from smooth- surface to rough-surface transitions, the transition time takes 4.5 s. The experimentally measurement results of speed- adjustment time after surface transition are useful for fast and stable recognition-system design.
{"title":"Surface Recognition and Speed Adjustment of Humanoid Robot Using External Control Circuit","authors":"S. Bhattacharya, A. Luo, S. Dutta, M. Miura-Mattausch, H. Mattausch","doi":"10.1109/ISDCS49393.2020.9263013","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263013","url":null,"abstract":"We propose a surface-recognition-based speed- adjustment system for humanoid robot during walking on different surfaces. Two different types of surfaces are considered in the reported experiment (example, rough and smooth surface). Force-sensors, classification unit and external- controller-circuits are applied for surface-recognition and speed-adjustment. For surface-recognition the Euclidean distance is used to calculate the nearest-neighbor reference pattern for the feature of the waking pattern generated online. The mean-absolute-value (MAV) feature vector is used to classify two different surfaces. To distinguish two different surfaces, the hardware accelerated decision-signals are generated across LEDs in the form of analog voltages (maximum peak voltage 212 mV for rough-surface and 147 mV for smooth surfaces respectively with detection time 2.8 s and 1.5 s). The external-controller-circuit is used for speed- adjustment using decision-signal coming from LED. It is observed that, when robot is moving from rough-surfaces to smooth-surfaces, the speed of the robot motion changes from 190 frames/stride (i.e. slow-speed) to 160 frames/stride (i.e. medium-speed) with 4.9 s transition time, whereas from smooth- surface to rough-surface transitions, the transition time takes 4.5 s. The experimentally measurement results of speed- adjustment time after surface transition are useful for fast and stable recognition-system design.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116542561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263003
Shivdeep, Sudip Ghosh, H. Rahaman
In the world full of visual content, digital image authentication has become an important concern. Digital image watermarking can play a key role in this regard. Though several techniques and algorithms exist in literature but color image watermarking techniques with its hardware implementation are few. The objective of this paper is to introduce a new algorithm for watermarking a color cover image using color watermark. The basic technique is to alter the pixel values of the cover image, based on the similarity between cover image and watermark. The amount of alteration can be controlled by a parameter called modulation index, which also decides the quality of cover image as well as that of extracted watermark image. A pseudo-noise code is used for embedding and extraction of the watermark, hence only authorized users having exact pseudo-noise code can extract the watermark. This is an invisible watermarking technique, so it doesn’t affect the appearance of the original image significantly. Furthermore, FPGA as well as ASIC based hardware implementation of the aforesaid algorithm is realized. For real-time application hardware realization is more efficient than software implementation. The proposed algorithm and its VLSI implementation have been compared with stat-of-art research work present in literature. Throughput of the proposed algorithm is high and it can also be used for digital video watermarking.
{"title":"A New Digital Color Image Watermarking Algorithm with its FPGA and ASIC Implementation","authors":"Shivdeep, Sudip Ghosh, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263003","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263003","url":null,"abstract":"In the world full of visual content, digital image authentication has become an important concern. Digital image watermarking can play a key role in this regard. Though several techniques and algorithms exist in literature but color image watermarking techniques with its hardware implementation are few. The objective of this paper is to introduce a new algorithm for watermarking a color cover image using color watermark. The basic technique is to alter the pixel values of the cover image, based on the similarity between cover image and watermark. The amount of alteration can be controlled by a parameter called modulation index, which also decides the quality of cover image as well as that of extracted watermark image. A pseudo-noise code is used for embedding and extraction of the watermark, hence only authorized users having exact pseudo-noise code can extract the watermark. This is an invisible watermarking technique, so it doesn’t affect the appearance of the original image significantly. Furthermore, FPGA as well as ASIC based hardware implementation of the aforesaid algorithm is realized. For real-time application hardware realization is more efficient than software implementation. The proposed algorithm and its VLSI implementation have been compared with stat-of-art research work present in literature. Throughput of the proposed algorithm is high and it can also be used for digital video watermarking.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122808406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263020
Joshua Roy Palathinkal, Yuvam Bhateja, Sudip Ghosh, H. Rahaman
As copyright protection is vital and indispensable, watermarking schemes are employed for securing digital data. We propose a novel (to the best of our knowledge) blind and invisible, semi-fragile image watermarking scheme for embedding coloured watermark inside a coloured cover image. The spatial domain embedding is implemented in such a way that modification made in the pixel values of the cover image is not noticeable by human perception. However, the watermark pixel values can be recovered using a unique decoding mechanism, which has been included in the paper. Extraction of the original cover image using the embedded image is also discussed. The obtained MATLAB implementation results are promising when compared to similar state-of-the-art research work.
{"title":"A New Blind Invisible and Semi-Fragile Colour Image Watermarking Scheme in Spatial Domain","authors":"Joshua Roy Palathinkal, Yuvam Bhateja, Sudip Ghosh, H. Rahaman","doi":"10.1109/ISDCS49393.2020.9263020","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263020","url":null,"abstract":"As copyright protection is vital and indispensable, watermarking schemes are employed for securing digital data. We propose a novel (to the best of our knowledge) blind and invisible, semi-fragile image watermarking scheme for embedding coloured watermark inside a coloured cover image. The spatial domain embedding is implemented in such a way that modification made in the pixel values of the cover image is not noticeable by human perception. However, the watermark pixel values can be recovered using a unique decoding mechanism, which has been included in the paper. Extraction of the original cover image using the embedded image is also discussed. The obtained MATLAB implementation results are promising when compared to similar state-of-the-art research work.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129027379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262997
D. Dey, Pradipta Roy, D. De
In this paper, we investigate the electrical doping dependent conductivity changes in Adenine and Thymine bio-molecular chain using Density functional Theory and Non-Equilibrium Green’s Function based first principle approach. The bio-molecular chain has been passed through GaAs multi walled nanotube electrodes. It has been identified that increasing electrical doping concentration increase the conductivity through the heterostructure bio-molecular chain. It is also found that the quantum transmission through this bio-molecular chain is also electrical doping dependent. The calculated Current-Voltage characteristics strongly induced due to the doping concentration that is applied at the two ends of the multi walled GaAs nanotube. It has been identified that a small increment in electrical doping leads to change a huge amount of current transmission through the Adenine-Thymine heterogeneous chain.
{"title":"A First Principle Approach to Investigate Electrical doping-Dependent Conductance Changes in Adenine-Thymine Hetero-structure Chain using GaAs Nanotube","authors":"D. Dey, Pradipta Roy, D. De","doi":"10.1109/ISDCS49393.2020.9262997","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262997","url":null,"abstract":"In this paper, we investigate the electrical doping dependent conductivity changes in Adenine and Thymine bio-molecular chain using Density functional Theory and Non-Equilibrium Green’s Function based first principle approach. The bio-molecular chain has been passed through GaAs multi walled nanotube electrodes. It has been identified that increasing electrical doping concentration increase the conductivity through the heterostructure bio-molecular chain. It is also found that the quantum transmission through this bio-molecular chain is also electrical doping dependent. The calculated Current-Voltage characteristics strongly induced due to the doping concentration that is applied at the two ends of the multi walled GaAs nanotube. It has been identified that a small increment in electrical doping leads to change a huge amount of current transmission through the Adenine-Thymine heterogeneous chain.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120955568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262986
A. Verma, Suruchi Sharma, Sneha Bharti, Manisha Bharti, B. Kaur
Dopingless tunnel field-effect transistor (DLTFET) has emerged to eliminate MOSFET as promising minimal-power applications in emerging technologies. While, throughout this paper, we produced a new DLTFET based charge plasma tunnel junction. A gallium arsenide (GaAs) pocket is positioned around across source and channel interface of the silicon film, increasing the likelihood of tunneling. Although GaAs energy bandgap seems to be significantly beyond a silicon energy bandgap, it does have fast electron mobility and minimal tunneling mass, contributing to enhanced current drivability at the interface. In contrast, with the standard DLTFET and tunnel junction engineered DLTFET (GaAs-DLTFET) we properly assessed the DC and analog/RF values in specific terms of energy band diagram, electric field, carrier concentrations, transfer characteristics, transconductance, parasitic capacitance, cutoff frequency. The simulation of the conventional DLTFET and proposed device (GaAs-DLTFET) has been performed using the ATLAS device simulator. The proposed device has shown an increased ON-current (~100 μA/μm) and improved subthreshold swing (~10.25 mV/decade). The excellent characteristics are demonstrated by GaAs-DLTFET and linearity parameters are analyzed to give the justification that a device is a worthy option for future high-frequency analog/RF applications with minimal use of operational power.
{"title":"Design of Tunnel Junction Engineered Dopingless TFET for Low power Applications","authors":"A. Verma, Suruchi Sharma, Sneha Bharti, Manisha Bharti, B. Kaur","doi":"10.1109/ISDCS49393.2020.9262986","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262986","url":null,"abstract":"Dopingless tunnel field-effect transistor (DLTFET) has emerged to eliminate MOSFET as promising minimal-power applications in emerging technologies. While, throughout this paper, we produced a new DLTFET based charge plasma tunnel junction. A gallium arsenide (GaAs) pocket is positioned around across source and channel interface of the silicon film, increasing the likelihood of tunneling. Although GaAs energy bandgap seems to be significantly beyond a silicon energy bandgap, it does have fast electron mobility and minimal tunneling mass, contributing to enhanced current drivability at the interface. In contrast, with the standard DLTFET and tunnel junction engineered DLTFET (GaAs-DLTFET) we properly assessed the DC and analog/RF values in specific terms of energy band diagram, electric field, carrier concentrations, transfer characteristics, transconductance, parasitic capacitance, cutoff frequency. The simulation of the conventional DLTFET and proposed device (GaAs-DLTFET) has been performed using the ATLAS device simulator. The proposed device has shown an increased ON-current (~100 μA/μm) and improved subthreshold swing (~10.25 mV/decade). The excellent characteristics are demonstrated by GaAs-DLTFET and linearity parameters are analyzed to give the justification that a device is a worthy option for future high-frequency analog/RF applications with minimal use of operational power.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"128 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130022256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9263000
F. A. Herrera, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, Y. Hirano, H. Mattausch
This paper presents compact modeling for the short-channel effect on the multi-gate MOSFET technology. The focus is given on the double-gate MOSFET, which provides a core of the multi-gate MOSFET. It is shown that the short-channel effect is caused by the potential minimum, which occurs at the source side. The modeling is done by considering the potential distribution along the channel through the source/drain-channel contributions explicitly. It has been verified that the model can reproduce the short-channel effect of 2D numerical simulation results with one model parameter describing the junction profile. The presented model is validated for several technologies considering channel doping, silicon and oxide thickness. Furthermore, an extension of this model is implemented considering the influence of the drain doping, namely for Low Drain doping MOSFET (LDMOS). Low drain doping effects are precisely included in the resistance effect as well as the short-channel effects, demonstrating a suppression of short-channel effects in LDMOS technology.
{"title":"Modeling of Short-Channel Effect on Multi-Gate MOSFETs for Circuit Simulation","authors":"F. A. Herrera, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, Y. Hirano, H. Mattausch","doi":"10.1109/ISDCS49393.2020.9263000","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9263000","url":null,"abstract":"This paper presents compact modeling for the short-channel effect on the multi-gate MOSFET technology. The focus is given on the double-gate MOSFET, which provides a core of the multi-gate MOSFET. It is shown that the short-channel effect is caused by the potential minimum, which occurs at the source side. The modeling is done by considering the potential distribution along the channel through the source/drain-channel contributions explicitly. It has been verified that the model can reproduce the short-channel effect of 2D numerical simulation results with one model parameter describing the junction profile. The presented model is validated for several technologies considering channel doping, silicon and oxide thickness. Furthermore, an extension of this model is implemented considering the influence of the drain doping, namely for Low Drain doping MOSFET (LDMOS). Low drain doping effects are precisely included in the resistance effect as well as the short-channel effects, demonstrating a suppression of short-channel effects in LDMOS technology.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115545578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262981
S. Yoshitomi
This paper reviews the development of compact modeling technology of MOSFETs for RF (Radio Frequency) and millimeter wave applications. Thanks to the recent renovation of measurement techniques it is possible to generate big data on the basis of automated S-parameter measurement. Accordingly, MOSFETs’ compact models are already capable of providing accurate statistical simulation by the use of big data. In this paper, unique approach to revise existing MOSFETs’ compact models is demonstrated. Our study has shown proposed model can give accurate statistical distribution of high frequency behavior of MOSFETs via single device level and circuit level.
{"title":"Combination of Transistors’ compact model and Big Data For successful Smart Factory","authors":"S. Yoshitomi","doi":"10.1109/ISDCS49393.2020.9262981","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262981","url":null,"abstract":"This paper reviews the development of compact modeling technology of MOSFETs for RF (Radio Frequency) and millimeter wave applications. Thanks to the recent renovation of measurement techniques it is possible to generate big data on the basis of automated S-parameter measurement. Accordingly, MOSFETs’ compact models are already capable of providing accurate statistical simulation by the use of big data. In this paper, unique approach to revise existing MOSFETs’ compact models is demonstrated. Our study has shown proposed model can give accurate statistical distribution of high frequency behavior of MOSFETs via single device level and circuit level.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124079484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-04DOI: 10.1109/ISDCS49393.2020.9262987
Anannya Bhattacharya, Susomon Dutta, Sreeparna Paul, Subhrajit Sikdar, S. Chattopadhyay
In the current work, UV-light sensing property of poly-crystalline Zinc-Tin-Oxide (ZnSnO3)nano-crystalloids grown by employing double-step chemical bath deposition technique has been investigated. The formation of cubic ZnSnO3 structure on p-Si [100] substrate has been confirmed by FESEM images. Crystallographic orientation and optical properties of such crystalloids are studied by X-ray diffraction, UV-VIS spectrophotometry and ellipsometric measurements. Absorption coefficient of the CBD-grown ZnSnO3 is obtained to be 2.1 × 105/m, at the wavelength region corresponding to its band gap of 3.6 eV. The current-voltage (I-V) characteristic under both dark and illuminated condition reveals the ability of the self-biased heterojunction device to be used as UV-ray photo-detector.
{"title":"Growth of ZnSnO3 nano-crystalloids on Sisubstrate by employing chemical bath deposition (CBD) technique for self-powered UV-light sensing applications","authors":"Anannya Bhattacharya, Susomon Dutta, Sreeparna Paul, Subhrajit Sikdar, S. Chattopadhyay","doi":"10.1109/ISDCS49393.2020.9262987","DOIUrl":"https://doi.org/10.1109/ISDCS49393.2020.9262987","url":null,"abstract":"In the current work, UV-light sensing property of poly-crystalline Zinc-Tin-Oxide (ZnSnO3)nano-crystalloids grown by employing double-step chemical bath deposition technique has been investigated. The formation of cubic ZnSnO3 structure on p-Si [100] substrate has been confirmed by FESEM images. Crystallographic orientation and optical properties of such crystalloids are studied by X-ray diffraction, UV-VIS spectrophotometry and ellipsometric measurements. Absorption coefficient of the CBD-grown ZnSnO3 is obtained to be 2.1 × 105/m, at the wavelength region corresponding to its band gap of 3.6 eV. The current-voltage (I-V) characteristic under both dark and illuminated condition reveals the ability of the self-biased heterojunction device to be used as UV-ray photo-detector.","PeriodicalId":177307,"journal":{"name":"2020 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125775289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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