A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992123
H. Nakamura, K. Imamiya, T. Himeno, T. Yamamura, T. Ikehashi, K. Takeuchi, K. Kanda, K. Hosono, T. Futatsuyama, K. Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, H. Hazama, M. Saito, H. Meguro, K. Conley, K. Quader, Jing Chen
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引用次数: 10

Abstract

A 125 mm/sup 2/ 1Gb NAND flash uses 0.13 /spl mu/m CMOS. The cell is 0.077 /spl mu/m/sup 2/. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.
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125mm /sup 2/ 1Gb NAND闪存，程序吞吐量10mb /s
125 mm/sup 2/ 1Gb NAND闪存使用0.13 /spl mu/m CMOS。细胞为0.077 /spl μ /m/sup 2/。改变芯片架构，减小芯片尺寸，实现10.6 MB/s的程序吞吐量和20 MB/s的读取吞吐量。片上页面复制功能为垃圾收集提供9.4 MB/s的吞吐量。
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
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