A 11-bit 1.2V 40.3μW SAR ADC with self-dithering technique

Abstract

This paper presents a low-power 11-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a self-dithering technique. The LSBs is employed as a dither to improve the resolution. Compared to converters that use the conventional dithering architecture, simulation results show that the proposed self-dithering technique improve the DNL performance with simplified hardware. The prototype is fabricated in 180nm 1P6M CMOS with MOM capacitor. At a 1.2-V supply and 1 MS/s, the post-layout simulation result shows an SNDR of 63.8 dB and consumes 40.3μW, and a figure of merit (FOM) of 32 fJ/conversion-step. The total area of the chip is 1 mm×1 mm.