{"title":"The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices","authors":"H. Tuinhout, Oliver Dieball","doi":"10.1109/ICMTS55420.2023.10094063","DOIUrl":null,"url":null,"abstract":"This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and highspatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS55420.2023.10094063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and highspatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.