Clock generator using factorial DLL for video applications

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929826

J. Bégueret, Y. Deval, O. Mazouffre, A. Spataro, P. Fouillat, E. Benoit, J. Mendoza

引用次数: 14

Abstract

This paper presents a clock generator dedicated to front-end processors for LCD and plasma monitor video applications. The topology is based on a factorial DLL, which can support all kind of standards (from VGA up to SXGA). Fabricated in a 2.5 V, 0.25 /spl mu/m, 6-metal CMOS VLSI process from STMicroelectronics, the maximum r.m.s. measured jitter is 17 ps. The power consumption is 17 mW at 200 MHz output frequency. The low cost area (0.08 mm/sup 2/) and the fully integrated structure make it well suited for such a video market.

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时钟生成器使用阶乘DLL用于视频应用程序

本文介绍了一种用于LCD和等离子体监控视频应用的前端处理器的时钟发生器。该拓扑基于一个阶乘DLL，它可以支持所有类型的标准(从VGA到SXGA)。采用意法半导体(STMicroelectronics)的2.5 V、0.25 /spl μ m、6金属CMOS VLSI工艺制造，测量到的最大有效值抖动为17 ps，在200 MHz输出频率下功耗为17 mW。低成本面积(0.08 mm/sup 2/)和完全集成的结构使其非常适合这样的视频市场。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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