{"title":"An implementation of MPEG-2 transport stream multiplexer","authors":"S.J. Kim, Jong-Seog Koh","doi":"10.1109/SIPS.1999.822343","DOIUrl":null,"url":null,"abstract":"In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.1999.822343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper.
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