Low cost flip chip package design concepts for high density I/O

Abstract

The semiconductor industry at large is migrating from wire bond packaging to flip chip packaging due to electrical performance requirements. With the removal of the highly resistive and inductive wire bonds, high-speed buses achieve well-controlled characteristic impedance for signal wave propagation and lower impedance for the power delivery network. However, a disadvantage of flip chip packaging is its lower input/output (I/O) routing density when compared to wire bond packaging. To meet the high I/O count for certain products, innovative flip chip bump patterns and creative routing options are needed. This paper will outline some innovative package design concepts on both die to package, defined as level 1 interconnect, and package to motherboard (MB), defined as level 2 interconnect, to increase the I/O signal routing density without increasing the package or MB cost.