Michele Bertasi, G. Di Guglielmo, F. Fummi, G. Pravadelli
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Abstract
The paper presents an automatic procedure for generating a particular kind of extended finite state machine, which allows a more uniform exploration of the state space of a design under verification. The proposed approach avoids the transition-incompatibility problem which typically arises in actual HW/SW-system descriptions. A EFSM-based ATPG, which exploits such a model, is able to more uniformly analyze the state space of the system with respect to using a generic EFSM.
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