A Unified UVM Methodology For MPSoC Hardware/Software Functional Verification

Abstract

Over the past few years the complexity of Multi-Processor System on Chip (MPSoC) designs increased drastically. This made product verification very challenging and illusive. In order to cope with design complexity, Universal Verification Methodology (UVM) associated with System Verilog Assertions (SVA) are used extensively to build up robust verification environments revealing design issues. This work introduces a new methodology verifying SoC design blocks in two modes: Stubbing mode, where all blocks serving the Design Under Test (DUT) are implemented as UVM active and passive agents; Physical hardware mode, where all blocks are physically running along with the firmware driver. A complete SoC system contains: processor, controller, and encryption engine is studied while implementing the proposed verification approach. Functionality check and coverage collection are performed through UVM scoreboard and subscriber respectively. The proposed approach provides the capability of verifying both hardware and firmware simultaneously in the simulation phase.