Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837540
M. Weißbrich, H. Blume, G. P. Vayá
In this paper, a heterogeneous controller system and its first-silicon ASIC implementation are presented, where the use of a programmable NanoController next to a general-purpose microcontroller enables more efficient and flexible power management strategies than typical timer-based, periodical power-up of a single microcontroller in state-of-the-art IoT devices. The NanoController features a compact, control-oriented 4-bit ISA, which is used to continuously pre-process data in order to decide when to power-up the microcontroller required for infrequent complex processing, e.g., encrypted wireless communication. Despite its programmability, the required silicon area and power consumption are very small and enable the use in the always-on domain of SoCs for energy harvesting platforms, instead of much simpler and constrained timer circuits. The first-silicon ASIC implementation of such a controller system using a 65nm UMC low-leakage process is presented and evaluated for a real home automation application intended to operate on harvested energy, i.e., electronic door lock, reducing the average power consumption of reference microcontrollers by up to 20x.
{"title":"A Silicon-Proof Controller System for Flexible Ultra-Low-Power Energy Harvesting Platforms","authors":"M. Weißbrich, H. Blume, G. P. Vayá","doi":"10.1109/mocast54814.2022.9837540","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837540","url":null,"abstract":"In this paper, a heterogeneous controller system and its first-silicon ASIC implementation are presented, where the use of a programmable NanoController next to a general-purpose microcontroller enables more efficient and flexible power management strategies than typical timer-based, periodical power-up of a single microcontroller in state-of-the-art IoT devices. The NanoController features a compact, control-oriented 4-bit ISA, which is used to continuously pre-process data in order to decide when to power-up the microcontroller required for infrequent complex processing, e.g., encrypted wireless communication. Despite its programmability, the required silicon area and power consumption are very small and enable the use in the always-on domain of SoCs for energy harvesting platforms, instead of much simpler and constrained timer circuits. The first-silicon ASIC implementation of such a controller system using a 65nm UMC low-leakage process is presented and evaluated for a real home automation application intended to operate on harvested energy, i.e., electronic door lock, reducing the average power consumption of reference microcontrollers by up to 20x.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121805886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837672
Adil Malik, C. Papavassiliou, S. Stathopoulos
In this paper we elaborate and verify a data-driven modelling approach, pertaining to the stochastic trajectory of the memristance upon the application of pulses. Our proposed approach is to model the memristor’s behaviour as a time-homogeneous Markov chain. We introduce a simplified method that estimates the states and the state transition probabilities of the model from device measurements. We show that such a memristor model, generally corresponds to an absorbing Markov chain, the physical implications of which are also discussed. We apply this modelling methodology to real-world Pt/TiO2/Pt memristors and present results that validate its effectiveness in capturing the stochastic features of these devices over various timescales.
{"title":"An Absorbing Markov Chain Model for Stochastic Memristive Devices","authors":"Adil Malik, C. Papavassiliou, S. Stathopoulos","doi":"10.1109/mocast54814.2022.9837672","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837672","url":null,"abstract":"In this paper we elaborate and verify a data-driven modelling approach, pertaining to the stochastic trajectory of the memristance upon the application of pulses. Our proposed approach is to model the memristor’s behaviour as a time-homogeneous Markov chain. We introduce a simplified method that estimates the states and the state transition probabilities of the model from device measurements. We show that such a memristor model, generally corresponds to an absorbing Markov chain, the physical implications of which are also discussed. We apply this modelling methodology to real-world Pt/TiO2/Pt memristors and present results that validate its effectiveness in capturing the stochastic features of these devices over various timescales.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122596038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837596
Imen Sansa, A. Nasri, H. Zairi
In this paper, a Metamaterial unit cell is proposed for microwave applications. The structure is made up of an outer ring with four capacitive loads and two inside parts perpendicularly connected with a square in the center. A set of unit cells are associated with the bowtie antenna to improve their performances using the Theroy of Characteristic Modes. By adding the Metamaterial, the antenna performances are improved, such as the gain which increased by 3 dB, and the bandwidth that can reach 49 %.
{"title":"Analysis and Design of Metamaterial Antenna using the Theory of Characteristic Modes","authors":"Imen Sansa, A. Nasri, H. Zairi","doi":"10.1109/mocast54814.2022.9837596","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837596","url":null,"abstract":"In this paper, a Metamaterial unit cell is proposed for microwave applications. The structure is made up of an outer ring with four capacitive loads and two inside parts perpendicularly connected with a square in the center. A set of unit cells are associated with the bowtie antenna to improve their performances using the Theroy of Characteristic Modes. By adding the Metamaterial, the antenna performances are improved, such as the gain which increased by 3 dB, and the bandwidth that can reach 49 %.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"95 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123362270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837491
Ioannis S. Kafetzis, L. Moysis, C. Volos, H. Nistazakis, J. Muñoz-Pacheco, I. Stouboulos
This work introduces an encryption scheme for gray-scale plain-text images, which is based on a chaotic map. Initially, the proposed chaotic map, which is a modification of the Renyi map, is introduced and is utilized in defining a Pseudo-Random Bit Generator. Subsequently, a finite automaton is introduced. This, in combination with the aforementioned PRBG defines the encryption strategy, that is, the order in which the rows and columns are encrypted. The proposed method is subjected to a number of statistical tests, to prove its resistance against common attacks.
{"title":"Automata-Derived Chaotic Image Encryption Scheme","authors":"Ioannis S. Kafetzis, L. Moysis, C. Volos, H. Nistazakis, J. Muñoz-Pacheco, I. Stouboulos","doi":"10.1109/mocast54814.2022.9837491","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837491","url":null,"abstract":"This work introduces an encryption scheme for gray-scale plain-text images, which is based on a chaotic map. Initially, the proposed chaotic map, which is a modification of the Renyi map, is introduced and is utilized in defining a Pseudo-Random Bit Generator. Subsequently, a finite automaton is introduced. This, in combination with the aforementioned PRBG defines the encryption strategy, that is, the order in which the rows and columns are encrypted. The proposed method is subjected to a number of statistical tests, to prove its resistance against common attacks.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A Reconfigurable Intelligent Surface (RIS) is a passive system node, envisioned as a new physical layer technology in sixth-generation (6G) infrastructure. A RIS enables smart propagation environments by tuning the signal reflection in real time. Reflection optimization is an active field of research, regarding the RIS integration into wireless networks. A real-time response is required, while the unit-modulus constraint on the phase shift introduced by RIS elements makes the optimization problem even more challenging. In this paper, both low-complexity and efficient, in terms of achievable rate, passive beamforming methods are evaluated over a frequency-selective fading channel. Practical aspects of a RIS, including binary phase shifts with unbalanced amplitudes and mutual coupling, are considered. A hardware-oriented reflection optimization method is proposed and is implemented on a Zynq UltraScale+ multiprocessor system-on-a-chip (MPSoC) device. The proposed architecture leads to an extremely low execution time, useful especially for high mobility scenarios, in which coherence time is a tough constraint.
{"title":"Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods","authors":"Dimitris Vordonis, Dimitris Kompostiotis, Vassilis Paliouras","doi":"10.1109/mocast54814.2022.9837634","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837634","url":null,"abstract":"A Reconfigurable Intelligent Surface (RIS) is a passive system node, envisioned as a new physical layer technology in sixth-generation (6G) infrastructure. A RIS enables smart propagation environments by tuning the signal reflection in real time. Reflection optimization is an active field of research, regarding the RIS integration into wireless networks. A real-time response is required, while the unit-modulus constraint on the phase shift introduced by RIS elements makes the optimization problem even more challenging. In this paper, both low-complexity and efficient, in terms of achievable rate, passive beamforming methods are evaluated over a frequency-selective fading channel. Practical aspects of a RIS, including binary phase shifts with unbalanced amplitudes and mutual coupling, are considered. A hardware-oriented reflection optimization method is proposed and is implemented on a Zynq UltraScale+ multiprocessor system-on-a-chip (MPSoC) device. The proposed architecture leads to an extremely low execution time, useful especially for high mobility scenarios, in which coherence time is a tough constraint.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129407097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837642
Amir E. Oghostinos, Kareem Moussa, Amr Elnaggar, Alaa AbdAlrhman, A. Soltan
Enhancing computer architecture performance is a significant concern for architecture designers and users. This paper presents a novel approach to computer architecture design by using an approximate adder with configurable accuracy in a single-cycle MIPS processor as a study case. Using approximate adders decreased the delay on the expense of the design area. Using approximate computing with the MIPS processor, the timing performance has been improved by 253.4% compared to the lookahead adder. It has been implemented and tested using System-Verilog.
{"title":"Single-Cycle MIPS Processor based on Configurable Approximate Adder","authors":"Amir E. Oghostinos, Kareem Moussa, Amr Elnaggar, Alaa AbdAlrhman, A. Soltan","doi":"10.1109/mocast54814.2022.9837642","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837642","url":null,"abstract":"Enhancing computer architecture performance is a significant concern for architecture designers and users. This paper presents a novel approach to computer architecture design by using an approximate adder with configurable accuracy in a single-cycle MIPS processor as a study case. Using approximate adders decreased the delay on the expense of the design area. Using approximate computing with the MIPS processor, the timing performance has been improved by 253.4% compared to the lookahead adder. It has been implemented and tested using System-Verilog.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131099180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837726
R. Schroedter, A. S. Demirkol, A. Ascoli, R. Tetzlaff, Eter Mgeladze, M. Herzig, S. Slesazeck, T. Mikolajick
In this paper, we present a compact SPICE model of an analog switching memristive device based on niobium oxide and investigate the functionality of the same as a synapse element through its compact model by utilizing it in a simulation of an 8x8 resistive crossbar array. Considering especially the von Neumann bottleneck for neural network computing tasks, memristive crossbar arrays offer a potential in-memory computing solution performing highly parallel matrix-vector multiplication and reducing the energy consumption. In particular, multi-level switching memristive devices with intrinsic self-compliance are predestined for crossbar operations. Based on experimental results of a bi-layer Ti/Al2 O3/Nb2O5/Ti stack, a compact physical model was recently derived, assuming an underlying Poole-Frenkel emission mechanism. High model accuracy in terms of I-V behaviors, dynamic route map and power exponent plots were demonstrated by fitting the nonlinear I-V relation and the state function to measurement data, verifying analog gradual switching for the voltage driven extended memristor. In this paper the SPICE implementation for the core memductance accompanied by a parallel and series resistor is introduced and its application for sense analysis via analog and multi-memristor circuit exploitation is presented. Adopting the SPICE model, the switching dynamics is investigated and discussed for performing synaptic potentiation and depression behavior in a potential crossbar application.
{"title":"SPICE Compact Model for an Analog Switching Niobium Oxide Memristor","authors":"R. Schroedter, A. S. Demirkol, A. Ascoli, R. Tetzlaff, Eter Mgeladze, M. Herzig, S. Slesazeck, T. Mikolajick","doi":"10.1109/mocast54814.2022.9837726","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837726","url":null,"abstract":"In this paper, we present a compact SPICE model of an analog switching memristive device based on niobium oxide and investigate the functionality of the same as a synapse element through its compact model by utilizing it in a simulation of an 8x8 resistive crossbar array. Considering especially the von Neumann bottleneck for neural network computing tasks, memristive crossbar arrays offer a potential in-memory computing solution performing highly parallel matrix-vector multiplication and reducing the energy consumption. In particular, multi-level switching memristive devices with intrinsic self-compliance are predestined for crossbar operations. Based on experimental results of a bi-layer Ti/Al2 O3/Nb2O5/Ti stack, a compact physical model was recently derived, assuming an underlying Poole-Frenkel emission mechanism. High model accuracy in terms of I-V behaviors, dynamic route map and power exponent plots were demonstrated by fitting the nonlinear I-V relation and the state function to measurement data, verifying analog gradual switching for the voltage driven extended memristor. In this paper the SPICE implementation for the core memductance accompanied by a parallel and series resistor is introduced and its application for sense analysis via analog and multi-memristor circuit exploitation is presented. Adopting the SPICE model, the switching dynamics is investigated and discussed for performing synaptic potentiation and depression behavior in a potential crossbar application.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133289861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837742
Lutz Schammer, Jan Runge, Paula Klimach, Goerschwin Fey
Automated tools help a designer to reduce the time and the effort required to understand details of an unfamiliar design. In this paper we show an approach using static analysis to identify instruction pipelines, which are key structures in processor hardware designs. We present two algorithms which identify pipeline structures. The first algorithm is based on a structural analysis using a graph representation of the design, while the second algorithm uses terms and phrases for pipelines as they are found in literature for a name-matching approach. The two algorithms successfully identified pipelines for e.g. Y86 and edge processor designs.
{"title":"Design Understanding: Identifying Instruction Pipelines in Hardware Designs","authors":"Lutz Schammer, Jan Runge, Paula Klimach, Goerschwin Fey","doi":"10.1109/mocast54814.2022.9837742","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837742","url":null,"abstract":"Automated tools help a designer to reduce the time and the effort required to understand details of an unfamiliar design. In this paper we show an approach using static analysis to identify instruction pipelines, which are key structures in processor hardware designs. We present two algorithms which identify pipeline structures. The first algorithm is based on a structural analysis using a graph representation of the design, while the second algorithm uses terms and phrases for pipelines as they are found in literature for a name-matching approach. The two algorithms successfully identified pipelines for e.g. Y86 and edge processor designs.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128659559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837774
Petros Kokotis, J. Vourvoulakis
During recent years, various hardware platforms were developed, each one suitable for use in different kind of applications. Platforms based on FPGAs, DSPs, GPUs, Single Board Computers, microcontrollers extend processing capabilities and functionality in comparison with traditional personal computers based on a single CPU. Furthermore, co-design combines advantages from different types of processing units, rendering such architectures more attractive to researchers. In this paper, we achieve acceleration of image processing algorithms using a hardware platform based on a Raspberry Pi Single Board Computer and a custom designed FPGA HAT (Hardware Attached on Top) for RPi. The FPGA HAT consists of a Cyclone 10LP device. The FPGA undertakes a computationally demanding load, such as robotic vision algorithms exploiting parallelism, while the RPi can apply higher level operations such as running ROS (Robot Operating System). In order to overcome bottleneck in exchanging data between RPi and FPGA, a 16-bit parallel customized protocol was developed from scratch. The achieved transfer rate was about 50 Mbytes/sec when multi threaded software was implemented for the RPi. An image edge detector was implemented in order to verify the system performance. When only the RPi was used, the processing rate was 48fps for images with resolution 512x512 pixels. RPi and FPGA co-design achieved processing rate 170fps for the same resolution images, which means an acceleration of about 350%. The proposed system was also evaluated in terms of power consumption.
{"title":"Acceleration of image processing algorithms based on a Single Board Computer and FPGA co-design","authors":"Petros Kokotis, J. Vourvoulakis","doi":"10.1109/mocast54814.2022.9837774","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837774","url":null,"abstract":"During recent years, various hardware platforms were developed, each one suitable for use in different kind of applications. Platforms based on FPGAs, DSPs, GPUs, Single Board Computers, microcontrollers extend processing capabilities and functionality in comparison with traditional personal computers based on a single CPU. Furthermore, co-design combines advantages from different types of processing units, rendering such architectures more attractive to researchers. In this paper, we achieve acceleration of image processing algorithms using a hardware platform based on a Raspberry Pi Single Board Computer and a custom designed FPGA HAT (Hardware Attached on Top) for RPi. The FPGA HAT consists of a Cyclone 10LP device. The FPGA undertakes a computationally demanding load, such as robotic vision algorithms exploiting parallelism, while the RPi can apply higher level operations such as running ROS (Robot Operating System). In order to overcome bottleneck in exchanging data between RPi and FPGA, a 16-bit parallel customized protocol was developed from scratch. The achieved transfer rate was about 50 Mbytes/sec when multi threaded software was implemented for the RPi. An image edge detector was implemented in order to verify the system performance. When only the RPi was used, the processing rate was 48fps for images with resolution 512x512 pixels. RPi and FPGA co-design achieved processing rate 170fps for the same resolution images, which means an acceleration of about 350%. The proposed system was also evaluated in terms of power consumption.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129325763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837528
{"title":"Authors Stat","authors":"","doi":"10.1109/mocast54814.2022.9837528","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837528","url":null,"abstract":"","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129088947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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