{"title":"A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC","authors":"Jixuan Xiang, Jian Mei, Hao-Hsuan Chang, Fan Ye","doi":"10.1109/ASICON.2013.6812049","DOIUrl":null,"url":null,"abstract":"This paper presents an 8-b 400-MS/s 2-b-per-cycle SAR ADC with a preset capacitive DAC, which is simulated in 65-nm CMOS process. This SAR ADC achieves rapid conversion rate and low power, leading SNDR to 48.9dB, SFDR to 57.8dB, and ENOB to 7.83 bits at 400-MS/s sampling rate and in 186MHz input signal. The ADC consumes 0.766mW, and the FoM is 7.9fJ/conversion-step at 400-MS/s sampling rate from a 1.2-V supply voltage.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 10th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2013.6812049","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents an 8-b 400-MS/s 2-b-per-cycle SAR ADC with a preset capacitive DAC, which is simulated in 65-nm CMOS process. This SAR ADC achieves rapid conversion rate and low power, leading SNDR to 48.9dB, SFDR to 57.8dB, and ENOB to 7.83 bits at 400-MS/s sampling rate and in 186MHz input signal. The ADC consumes 0.766mW, and the FoM is 7.9fJ/conversion-step at 400-MS/s sampling rate from a 1.2-V supply voltage.
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