W. Chakraborty, P. Shrestha, A. Gupta, R. Saligram, S. Spetalnick, J. Campbell, A. Raychowdhury, S. Datta
{"title":"Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing","authors":"W. Chakraborty, P. Shrestha, A. Gupta, R. Saligram, S. Spetalnick, J. Campbell, A. Raychowdhury, S. Datta","doi":"10.1109/vlsitechnologyandcir46769.2022.9830483","DOIUrl":null,"url":null,"abstract":"Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,1~75μA) with read margin (ΔIRead=IRead,1-IRead,0) ~14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (~8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,1~75μA) with read margin (ΔIRead=IRead,1-IRead,0) ~14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (~8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.