Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing

W. Chakraborty, P. Shrestha, A. Gupta, R. Saligram, S. Spetalnick, J. Campbell, A. Raychowdhury, S. Datta
{"title":"Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing","authors":"W. Chakraborty, P. Shrestha, A. Gupta, R. Saligram, S. Spetalnick, J. Campbell, A. Raychowdhury, S. Datta","doi":"10.1109/vlsitechnologyandcir46769.2022.9830483","DOIUrl":null,"url":null,"abstract":"Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,1~75μA) with read margin (ΔIRead=IRead,1-IRead,0) ~14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (~8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,1~75μA) with read margin (ΔIRead=IRead,1-IRead,0) ~14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (~8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
低温计算中用于高速缓存的1T SiGe浮动体内存
低温计算需要高密度的片上高速缓存,具有低延迟、高带宽和节能访问,以增加缓存命中并最大化处理器性能。在这里,我们实验证明了在1T SiGe浮动体RAM (FBRAM)中使用77K的22nm FDSOI晶体管进行高速多比特存储操作,用于低温缓存应用。在77K下,1T SiGe FBRAM电池(W/LG=170nm/20nm)显示:(a)记录的写入时间为1012。阵列级基准测试显示,与6T SRAM相比,1T SiGe FBRAM具有8.3倍的内存密度,读/写能量增加2.3倍/1.8倍,读/写延迟3.3倍/1.7倍,能量延迟产品(EDP) 4.6倍,缓存大小为16MB, 77K。考虑到冷却能源成本,与300K 6T SRAM相比,FBRAM的EDP降低了60%。因此,SiGe FBRAM是高性能低温计算中L2/L3缓存的一个有前途的选择。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1